Coaxial Through-Package-Vias (TPVs) for Enhancing Power Integrity in 3D Double-side Glass Interposers Gokul Kumar, P. Markondeya Raj, Jounghyun Cho*, Saumya Gandhi, Parthasarathi Chakraborti, Venky Sundaram, Joungho Kim* and Rao Tummala 3D Systems Packaging Research Center, Georgia Institute of Technology * Terahertz Laboratory, KAIST, Daejeon, South Korea Email: gokul.kumar@gatech.edu ABSTRACT Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch as TSVs in Si, have been proposed to achieve high bandwidth between logic and memory with benefits in cost, process complexity, testability and thermal over 3D IC stacks with TSV. However, such a 3D interposer introduces power distribution network (PDN) challenges due to increased power delivery path length and plane resonances. This paper investigates the use of coaxial through-package-vias (TPVs) with high dielectric constant liners as an effective method to deliver clean power within a 3D glass package, and provides design and fabrication guidelines to achieve the PDN target impedance. The Coaxial TPV structure is simulated using electromagnetic (EM) solvers and a simplified equivalent circuit model to study via impedance and parasitics. Test vehicles with anodized tantalum oxide capacitors were fabricated in ultra-thin, 100μm thick glass interposers to demonstrate process feasibility, with a capacitance density of 5 nF/mm 2 . Self-impedance (Z11) of a 3D glass interposer containing the coaxial TPVs was analyzed with variations in (a) Via location, (b) Number of coaxial vias, and (c) Via capacitance and stack-up, to provide optimal PDN design guidelines. Based on the above parameters, the added decoupling vias achieved more than 30% impedance suppression over multiple resonance frequencies between 0.5- 6 GHz, providing an effective and flexible PDN design method for double-side 3D glass interposers. I. INTRODUCTION Logic and memory stacking with through silicon vias (TSV) to form 3D ICs, with much higher interconnect density than the current package-on-package (PoP) stacking, has been proposed and is being developed to meet ultra-high bandwidth (25-100GB/s) demands of smart mobile systems with lower power consumption and miniaturization. However, the adoption of these 3D ICs has been delayed by many challenges that include thermal issues, testability and high cost. A simpler approach to achieve this high bandwidth using ultra-thin 3D glass packages has been proposed and fabricated by Georgia Tech [1] [2], which results in elimination of complex and costly TSVs in the logic die, as shown in Figure 1. Such a 3D glass approach uses an ultra-thin, 30-50μm glass interposer with stacked memory on one side and logic IC on the other side, interconnected by through package vias (TPVs) at the same pitch as TSVs in Si, and SMT mounted onto the printed wiring board (PWB) through solder ball interconnections [3]. While this technology offers cost, testability and thermal advantages over 3D IC stacking, it introduces a new challenge in power delivery, directly attributable to the long PDN path through lateral power-ground (P/G) planes. In addition, multi-mode plane resonances in glass interposers, that are common to high- resistivity substrates including organic packages, require careful PDN design. Figure 1 : Approaches for high bandwidth 3D-integration Figure 2 : 3D Glass interposer PDN with coaxial Vias as distributed decoupling capacitors This paper, for the first time, integrates high-dielectric constant materials into TPVs in ultra-thin glass interposers to improve the PDN performance of double sided 3D interposers, and the techniques presented here can also be applied to single- chip 2D packages and multi-chip 2.5D interposers. Figure 2 illustrates the major power delivery challenges in 3D glass interposers and the proposed structure with coaxial TPVs to address some of these challenges. The coaxial TPVs with high dielectric constant thin films between the power and ground via conductors form ultra-miniaturized decoupling capacitors along the package power path. This distributed capacitance, placed very close to the active die, acts as charge reservoirs and presents an improved power delivery solution without ESL limitations or additional space requirements. The authors previously reported the PDN characteristics of 3D double-side interposers with reduced power/ground ball Glass interposer PCB Logic Memory Memory Memory Memory BGA TSV TPV Silicon Interposer or Org. Pkg PCB Logic Memory Memory Memory Memory BGA TSV 3D Glass Interposers with TPVs 3D ICs with TSVs Memory Stack PCB Logic P/G BGA Distributed Coaxial P/G TPVs as Decap P/G planes Lateral PDN Path 978-1-4799-2407-3/14/$31.00 ©2014 IEEE 541 2014 Electronic Components & Technology Conference