Microprocessors and Microsystems 49 (2017) 28–43 Contents lists available at ScienceDirect Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro A collision management structure for NoC deployment on multi-FPGA Atef Dorai a,b,c,∗ , Virginie Fresse a , Catherine Combes a , El-Bay Bourennane d , Abdellatif Mtibaa c a Hubert-Curien laboratory, UMR CNRS 5516, Jean-Monnet University of Lyon, France b INRIA/IRISA, University of Rennes-1, Lannion France c EmicroE Laboratory LR99ES30, University of Monastir, Tunisia d Le2i laboratory UMR CNRS 6306, University of Bourgogne, Dijon, France a r t i c l e i n f o Article history: Received 3 March 2016 Revised 12 December 2016 Accepted 17 January 2017 Available online 20 January 2017 Keywords: Traffic collision Network-on-chip Inter-FPGA communication Multi-FPGA Resource dimensioning a b s t r a c t With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA plat- forms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs re- quiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs. In this paper, we propose a novel architecture for inter-FPGA collision management in the Network- on-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architec- ture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA plat- forms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions. © 2017 Elsevier B.V. All rights reserved. 1. Introduction The integration of several cores into a System-on-Chip (SoC) be- comes higher and gives rise to new challenges [1]. For example, Intel has developed a co-processor called x86 Knights Corner that has 72 cores [2] and NVIDIA designs has announced a multicore- chip called Quadro M6000 with 3072 CUDA cores [3]. SoCs, such as the previously presented ones, that use a Network-on-Chip (NoC) communication infrastructure are the most efficient architectures for applications with hundreds of cores. The NoC is needed to sup- port a lot of parallel data transmissions and high bandwidths. A ∗ Corresponding author. E-mail addresses: atef.dorai@univ-st-etienne.fr (A. Dorai), virginie.fresse@univ- st-etienne.fr (V. Fresse), catherine.combes@univ-st-etienne.fr (C. Combes), ebourenn@u-bourgogne.fr (E.-B. Bourennane), abdellatif.mtibaa@enim.rnu.tn (A. Mtibaa). NoC structure ensures high scalability, high performance and low power consumption [5]. Emulating a SoC or a NoC only is often done one on Field Programmable Gate Arrays devices (FPGAs). FP- GAs are widely used for functional verification of complex logic de- signs, as their speed is 100–1,000 times faster than software sim- ulations (i.e. simulations using a PC). However, one major limitation with the use of FPGA is that its gate capacity is below the capacity required by large SoCs using a NoC. [4] shows that the recent designs of NoC can be so large that resources of a single FPGA are not enough. Although Moore’s law indicates that the number of transistors on a chip doubles approx- imately every two years, the larger SoC requires more and more resources that cannot be handled by one single chip. A multi-FPGA platform is therefore the most appropriate solution. Few research works have evaluated the performances of a large SoC since implementing a large SoC on a multi-FPGA platform is very challenging [6,10]. The number of FPGAs depends on the size of the prototyped SoC or NoC, which ranges from few FPGAs [8] up http://dx.doi.org/10.1016/j.micpro.2017.01.006 0141-9331/© 2017 Elsevier B.V. All rights reserved.