IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, VOL. 4, NO. 3, MAY 2014 391 77–110 GHz 65-nm CMOS Power Ampliﬁer Design Kun-Long Wu, Kuan-Ting Lai, Robert Hu, Christina F. Jou, Dow-Chih Niu, and Yu-Shao Shiao Abstract—This paper details the development of our millimeter- wave wideband power ampliﬁer design. By treating the power combiner as an impedance transformer which allows different loading impedance to be taken into account, a compact wideband power-combining network can be constructed. With small trans- mission-line attenuation being sustained and maximum output power easily extracted from the transistors over the 77–110 GHz frequency range, a power ampliﬁer can then be designed using 65-nm CMOS process to cover the whole W-band. In the on-wafer measurement, the gain is around 18 dB, the output reﬂection coefﬁcients is below 10 dB, and the output-referred 1 dB com- pression point can reach 12 dBm at 1.2 V bias condition; when the bias is increased to 2.5 V, a 18 dBm output power is recorded. To our knowledge, this is the ﬁrst CMOS power ampliﬁer that covers the whole W-band. Index Terms—CMOS, impedance transformation, millimeter- wave, power ampliﬁer, power combining, wideband. I. INTRODUCTION I N THE DESIGN of silicon power ampliﬁers, several tech- niques have been employed to increase the output power level such as current combining where the Wilkinson power combiner is probably the most well-known [1]–[6], voltage combining [7]–[13], or the phase-array spatial combining [14]–[16]. With very low-loss antennae, which need to be fabricated separately from the ampliﬁer circuit, the radiation efﬁciency and aggregate power level of the phase-array power ampliﬁer system can be impressive. Since the current or voltage combining approach can be developed independently and then integrated with the phase-array technique on the system level, we would like to explore in this paper the possibility of de- signing an optimized millimeter-wave wideband PA circuit using either current- or voltage-combining for maximum output power delivery over the intended bandwidth, which is 77–110 GHz in this case. Manuscript received November 17, 2013; revised February 07, 2014; ac- cepted March 31, 2014. Date of current version April 29, 2014. This work was supported in part by National Science Council of Taiwan, Republic of China, under Contracts NSC 101-2221-E-009-170, NSC 100-2623-E-009-005-D, NSC 100-2627-E-002-003, and NSC 99-2627-E-002-003. K.-L. Wu and C. F. Jou are with the Department of Electrical Engi- neering, National Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: marskenny2004@yahoo.com.tw). K.-T. Lai and R. Hu are with the Department of Electronics Engi- neering, National Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: roberthuroberthu@gmail.com). D.-C. Niu is with Chung-Shan Institute of Science and Technology, Taoyuang, Taiwan. Y.-S. Shiao is with National Nano-Device Laboratories, Hsinchu 30078, Taiwan. Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identiﬁer 10.1109/TTHZ.2014.2315451 As with the loading impedance and the total number of ampliﬁcation branches, the equivalent loading impedance for each branch will be in the current-combining case and in voltage-combining. Therefore, it is the impedance-di- viding property in voltage combining that allows large current, and thus power, extraction from individual transistor. This pre- ferred large current swing is more obvious in the submicron era, where low breakdown voltage tends to limit the available output power of each transistor. However, the complexity of cir- cuit layout and the parasitics of the transformer itself will make the voltage-combining technique to be narrow-band. By con- trast, the simplicity in current-combining layout renders the de- sign of millimeter-wave wideband PA a less daunting task as long as the constraint can be properly handled. In this paper, by treating the combining circuit as impedance trans- former, it is found that, under parallel- loading condition, a very compact and low-loss current combiner can be constructed over wide bandwidth. At the combiner’s output, a broadband network will provide this speciﬁc value from the nominal 50 loading impedance; while at its input, another matching circuit can maximize the power extraction from the transistor. Theoretical analysis and simulation regarding this capacitive- loading power combiner and the matching circuits are carried out ﬁrst; power combiners for other loading conditions, such as parallel- , series- , and series- , will also be compared and discussed. A 77–110 GHz 65-nm, CMOS power ampliﬁer is then designed using this combining technique and measured on-wafer. Though the delivered output power is still lower than those of narrow-band ampliﬁers, this 77–110 GHz PA demon- strates the potential of silicon circuits in millimeter-wave wide- band applications. II. ANALYSIS OF CAPACITIVE POWER-COMBINING CIRCUIT Fig. 1(a) shows the schematic of an ideal -way power com- bining circuit where the output loading is a parallel cir- cuit. With identical (common-mode) input signals, an equiv- alent single-branch conﬁguration can be constructed, as illus- trated in Fig. 1(b). By assuming the line impedance to be and its electrical length , the corresponding input impedance can be derived as (1) with (2) If we treat the power combining circuit as a multi-input single-output impedance transformer that allows the loading 2156-342X © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.