An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, and Bernabé Linares-Barranco, Fellow, IEEE Abstract—This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage differential signaling (LVDS) and two handshaking lines. Each event is represented by a 32-bit word. Two extra preamble bits are used for alignment. Transmission clock is embedded in the data using Manchester encoding. As opposed to conventional LVDS links, the presented approach allows to stop physical communication between data events, so that no “comma” characters need to be transmitted during these pauses. As soon as a new event needs to be trans- mitted, the link recovers immediately thanks to a built-in control voltage memorization circuit. As a result, power consumption of the serializer and deserializer circuits is proportional to data event rate. The approach is also highly tolerant to clock jitter, due to the asynchronous nature and the Manchester encoding. A chip test prototype has been fabricated in standard 0.35 m CMOS including a pair of Serializer and Deserializer circuits. Maximum measured event transmission rate is 15 Meps (mega events per second) for 32-bit events, with a maximum bit transmission speed of 670 Mbps (mega bits per second). Index Terms—Address event representation (AER), asyn- chronous circuits, asynchronous communications, clock data recovery (CDR), event-driven processing, low voltage differential signaling (LVDS), Manchester encoding, neuromorphic circuits and systems, serial AER, serial interchip communication. I. INTRODUCTION A DDRESS EVENT representation (AER) is a well-estab- lished technology among neuromorphic engineers, pro- posed initially 20 years ago [1], [2]. AER exploits asynchronous principles [7], [8], and has been used fundamentally in vision (retina) sensors, for purposes such as simple light intensity to frequency transformations [12], [13], time-to-first-spike coding [14], [15], foveated sensors [16], spatial contrast [17]–[20], temporal contrast [12], [21]–[24], motion sensing and compu- tation [5], and combined spatial and temporal contrast sensing [25], [26]. AER has also been used for auditory systems [3], [4], [27]–[29], competition and winner-takes-all networks This work was supported by the EU under Grant 216777 (NABAB), Spanish grants (with support from the European Regional Development Fund) TEC2006-11730-C03-01 (SAMANTA2), TEC2009-106039-C04-01 (VULCANO), and Andalusian grant P06TIC01417 (Brain System). The work of C. Zamarreño-Ramos was supported by an FPU scholarship. This paper was recommended by Associate Editor V. Gaudet. The authors are with the Instituto de Microelectrónica de Sevilla (IMSE- CNM-CSIC). 41092 Sevilla, Spain (e-mail: bernabe@imse-cnm.csic.es). [30], [31], and even for systems distributed over wireless networks [32]. But AER has also been employed for post- sensing event-driven processing, emulating biological cortical structures. Fixed-kernel [33], [34] and programmable-kernel [35]–[37] 2-D convolution chips have been reported, as well as reconfigurable multimodule AER processing systems [30], [38], [39]. The Appendix briefly explains the operation of a typical AER sensor or processor. AER systems are clearly growing in complexity, and neuro- morphic researchers are reporting work towards hierarchically structured multimodule AER systems [30], [38]–[42], using ei- ther a globally shared AER bus [30], [39], a global bus config- ured as a grid of physical links [43], many independent point-to- point plugged-in AER links between modules [38], or proposing multimodule multilink AER systems with local smart routing schemes [40], [41], [44]. This latter approach shows great po- tential for high degree of topological reconfigurability. The ten- dency seems to be towards individual AER modules, each with a relatively high number of AER links and with some local intelli- gence to reroute on-transit events, process incoming events, and send out newly produced events. Fig. 1 illustrates this philos- ophy. Fig. 1(a) shows a target PCB hosting 120 AER processing modules. Fig. 1(b) depicts an individual module communicating bidirectionally with other four neighboring modules, resulting in eight point-to-point links. This multichip assembly philos- ophy requires to minimize power and pin-count per module and link. For example, the solution proposed in the present paper uses 4 lines per link (a 2-line high-frequency differential micro strip and two lower frequency handshaking lines), and power consumption scales down with event rate. Also, as overall system complexity grows, the amount of in- formation to transmit per event also grows. In general, an event may carry information about local coordinates within a module, ID of sending and/or receiving module, as well as extra param- eters or commands [40], [41], [44]. Thus, AER links should be capable to transmit large number of bits, and in practice it would be very desirable to have this number of bits per event config- urable for each link. Present-day AER sensors transmit at the most 20 bit per event [3]–[6], [9]–[29]. For the example PCB in Fig. 1(a) we would need 7 extra bits to code an ID for each module, plus some extra bits for optional parameters. Conse- quently, a target event bit number of 32 seems quite realistic for a multimodule AER system. Most of reported AER sensor and processing chips use parallel AER interchip communication ports with a fixed number of bits. However, using parallel AER communication for a module as in Fig. 1 results in an exces- sive number of pins and a huge power consumption. An alter- native solution is to transmit “event subwords” serially through