Indian Journal of Engineering & Materials Sciences Vol. 21, April 2014, pp. 233-240 Reconfigurable architecture of RNS based high speed FIR filter J Britto Pari* & S P Joy Vasantha Rani Department of Electronics Engineering, MIT Campus, Anna University, Chennai 600 025, India Received 28 January 2013; accepted 3 January 2014 In this paper, a high speed reconfigurable FIR filter with multiple taps using accumulator based radix-4 multiplier is proposed. The 3n-bit binary input is converted into three residues using binary to residue number system (RNS) converter and then processed in three FIR sub filters constructed in direct form. The filter structure is implemented with a multiply and accumulate (MAC) architecture using accumulator based radix-4 multiplier. The reconfigurable structure is achieved by combining power of two (PoT) FIR sub modules and the coefficients are altered during runtime. The proposed design is tested and implemented for 20-tap FIR filter. The architecture is implemented using VHDL and synthesized using Altera cyclone II EP2C35F672C6. The performance results show that the architecture achieves low power and high speed and variable tap flexibility. Keywords: FIR filter, Residue number system, Higher radix multiplier, Reconfigurable architecture, Power of two FIR filters are the most important in the design aspect of low power digital signal processing system in multimedia and mobile computing applications. Recently with the advent of software defined radio (SDR), the research has been focused on reconfigurable realization of FIR filters 1-5 due to the need of flexibility and low complexity. The reconfigurable FIR filters are generally designed based on programmable multiply-accumulate (MAC) architecture 4 , distributed arithmetic (DA) based architecture 1,5 or programmable shift method (PSM) 3 . The performances of the designs are analyzed in terms of hardware complexity, low power and high speed. The DA based architectures presented in refs 1,5 occupy larger area. The digit based reconfigurable architecture presented in ref. 2 provides a flexible and low-power solution to FIR filters with a wide range of precision and tap length. The work presented in ref. 4 shown that even though the programmable MAC architectures or dedicated architectures consume low power with the reduced supply voltage, they require large area. The filter is intended to perform as a digital front-end of SDR which requires highest sampling frequency while designing the channel filters. Many researchers 1-5 addressed the problem of reducing the hardware complexity, low power and increase speed of operation. PSM based reconfigurable architecture 3 achieves low complexity and considerable speed due to the presence of programmable shifters, but not useful for channel filter design. The speed of operation and parallelism of digital filters is improved by the concept of residue number system (RNS) 6,7 . In RNS based system, a set of moduli is used to convert the binary system to RNS system for efficient implementation of arithmetic operations in which the carry propagation is minimized by breaking an operation into smaller operations. Several researchers 8-10 have attempted to implement the RNS based digital filter. In n bit or 2n bit adder based implementations for residue converters described in ref. 11 surmounts the moduli sets used in LUT based approach 12 , on comparing the above methods, the former takes advantage of achieving improvement in both area and speed. The efficient implementation of multiplier decides the speed and power in FIR filters 13-15 . Booth’s bit pair recoding algorithm allows faster multiplication by recoding the number that is multiplied 16 and is used to reduce the number of partial products. Radix-4 based Booth multiplier is used for reducing partial products to n/2 16 where n is the number of bit. Radix multipliers are commonly used in FIR filter design because of lesser number of computations, lesser adders and lesser iterative steps. When comparing with serial multiplier, radix multiplier occupies lesser space. In this paper, the FIR filters are implemented using accumulator based radix-4 multiplier whose inputs are in residue format and coefficients of multiplier are ______________________ *Corresponding author (E-mail: brittopari@yahoo.co.in)