IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 14, NO. 5, MAY 1995 607 C. H. Stapper, “Defect density distribution for LSI yield calculations,” IEEE Trans. Electron Devices, vol. ED-20, pp. 655457, July 1973. -, “Large-area fault clusters and fault tolerance in VLSI circuits: A review,” ZBMJ. Res. Develop., vol. 33, pp. 162-177, Mar. 1989. -, “Statistics associated with spatial fault simulation used for eval- uating integrated circuit yield enhancement,” ZEEE Trans. Computer- Aided Design, vol. 10, pp. 399-406, Mar. 1991. I. Koren, Z. Koren, and C. H. Stapper, “A unified negative-binomial distribution for yield analysis of defect-tolerant circuits,’’ IEEE Trans. Comput., vol. 42, pp. 724733, June 1993. P. C. Maxwell and R. C. Aitken, ‘The effectiveness of IDDQ, functional and scan tests: How many fault coverages do we need?’ in Proc. IEEE Int. Test Con$, Sept. 1992, pp. 168-177. F. Corsi, S. Martino, and T. W. Williams, “Defect level as a function of fault coverage and yield,” in Proc. European Test Con$, 1993, pp. 507-508. J. J. T. Sousa, F. M. GonGalves, J. P. Teixeira, and T. W. Williams, “Fault modeling and defect level prediction in digital IC’s,” in Proc. European Design Test Con$, Feb. 1994, pp. 436-442. P. C. Maxwell, R. C. Aitken, and L. M. Huisman, “The effect on quality of nonuniform fault coverage and fault probability,” in Proc. IEEE Int. Test Con$, Sept. 1994, pp. 739-746. Analog Checkers with Absolute and Relative Tolerances Vladimir Kolaiik, Salvador Mir, Marcel0 Lubaszewski, and Bemard Courtois Abstract-The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code falls out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattem generator for off-line testing of the checkers is proposed. I. INTRODUCTION High safety systems require that the functions they perform are on- line checked in order to prevent that the system moves to a dangerous state after an error has occurred. The design of integrated circuits embedding concurrent error detection capabilities is a problem which has been widely addressed in the digital field. Although some research in this direction has already been reported for analog parts, much work remains to be done in terms of safety designs for mixed (analog- digital) applications. This is a topic which has raised much interest in the space, aeronautics, railway, automotive and other industries. Manuscript received September 1, 1994; revised January 25, 1995. This work is part of the ARCHIMEDES ESPRIT-I11 Basic Research Project, funded by the CEC under Contract 7107. S. Mir is under grant from Comisi6n Interministerial de Ciencia y Tecnologia (CICYT), Spain. This paper was recommended by Guest Editors W. Maly and Y. Zorian. V. Kolafik was with the TIMMNPG Laboratory, F-38031 Grenoble, France. He is now with the Department of Microelectronics, Technical University of Bmo, CZ 602 00 Bmo, Czech Republic. S. Mir and B. Courtois are with the TIMMNPG Laboratory, F-38031 Grenoble, France. M. Lubaszewski was with the TIMMNPG Laboratory, F-38031 Grenoble, France. He is now with the Federal University of Rio Grande Do SUI, Brazil. IEEE Log Number 9410360. Analogue Fun c tl o n aI Encoded inputs Analogue -----f -_it Checker I_) Enor tndtcatlon Fig. 1. Self-checking circuit. Similarly to the digital world, the on-line test of analog circuits has to be based on some degree of (time or space) redundancy which stems from the use of a code. The input signal (with its related coding) is processed by the functional system. A circuit called a checker is then used for verifying whether the coding of the intermediate and output signals in the signal path of the functional system remain within a given valid code space. A good code for a given circuit under test would be such that, for all faults in a given fault model of the circuit, the inputs of the checker receive signals whose corresponding code does not belong to the valid code space of the circuit. The structure of self-checking circuits which implement this principle is shown in Fig. 1. Previous works on this field discussed the implementation of duplicated [ 11 and partially duplicated analog systems [2], presented a checksum approach applicable to state variable systems [3], [4], proposed an on-line test of a current-mode analog-to-digital converter based on the time replication of the function [5], addressed theoretical aspects of the design of finitely self-checking circuits and applied this theory to built-in current sensors [6], proposed error tolerating codes suitable for analog-to-digital and digital-to-analog converters [7], and, finally, studied the on-line [8] and off-line [12] test of fully differential circuits based on balance checking. Since each work was based on a different analog code, different checkers were proposed which suited the coding in use. The design of analog checkers for on-line testing duplicated and fully differential analog circuits is investigated in this paper. We show that these inherently redundant analog circuits result in the use of an analog code. The design of analog checkers for verifying the coding of analog signals in these types of circuits is presented. The checkers take into account the fact that in the analog world there is a tolerance margin inside which circuits are considered to be operational. Abso- lute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. The case of absolute tolerance margins is first considered. A CMOS implementation (AMs-Austria Mikro Systeme Intemational-1.2 pm double metal double poly) that is based on an open-loop operational amplifier is presented. A test pattem generator for off-line exercising of the checkers is proposed. Fault simulation results indicate that the properties of the checker are maintained for single hard faults in all elements of the checker. Analog checkers considering relative tolerance margins are considered next. An implementation of a checker suitable for sample- and-hold differential circuits is presented. All checkers provide a digital error indication output for the sake of compatibility with existing digital self-checking circuits. Finally, the paper concludes with a comparison of the different checkers between themselves and with respect to other existing checkers. 11. CHECKER FUNCTIONAL SPECIFICATION The duplication and the differential analog codes were previously introduced in [2] and [ 81, respectively. A graphical representation 0278-0070/95$04.00 0 1995 IEEE