TGLD: A 16-Channel Charge Readout Chip for the PHENIX Pad Chamber Detector Subsystem at RHIC 1 W. L. Bryan 2 , U. Jagadish 2 , C. L. Britton 2 , S. S. Frank 2 , M. N. Ericson 2 , M. L. Simpson 2 , G. R. Young 2 , L. G. Clonts 2 , R. S. Smith 3 , Anders Oskarsson 4 , Tommy Mark 5 , Ed Obrien 6 , Vicki Greene 7 2 Oak Ridge National Laboratory, Oak Ridge, TN 3 IBM, Research Triangle Park, NC 4 University of Lund, Lund, Sweden 5 McGill University, Montreal, Canada 6 Brookhaven National Laboratory, Upton, NY 7 Vanderbilt University, Nashville, TN Abstract This paper describes TGLD, a charge readout chip for the PHENIX Pad Chamber (PC) subsystem at Brookhaven National Laboratory’s Relativistic Heavy Ion Collider (RHIC) in Upton, NY. Due to the PC’s high channel density, the TGLD and associated circuitry operate within the active detector region as permanent, zero access components, with remote set-up and test during collider operation. The TGLD design accommodates varying pad capacitance and charge gain for three detector subassemblies that detect particles at three different distances from the PHENIX collision vertex. The design also provides adjustable discrimination thresholds from MIP/10 to 2 MIP (Minimum Ionizing Particle). Three TGLD chips operate with a complimentary digital memory unit (DMU) to form 48 channel low power, low mass, readout cards. Partitioning of readout electronics and address control for robust remote operation are discussed. Component and system test results are also reported. I. INTRODUCTION The PHENIX experiment is a large and complex, multi- detector experiment. It is comprised of ten different detector subsystems designed to track and measure the energies of heavy ion collisions with ion masses up to gold. The PHENIX PC subsystem consists of three sections, PC1, PC2 and PC3, with an east and west arm for each section. These three tracking detector sections are each positioned at different radial distances from the collision vertex. The PC subsystem accounts for 207,360 of the approximately 600,000 detector channels in PHENIX. Since the PC tracking detectors are sandwiched between multiple calorimeters, it is important that the PC’s radiation absorption be as low as possible, to avoid energy measurement degradation in adjoining calorimeters. Additionally, the large number of PC detector elements preclude bringing pad wire connections outside the detector’s 1 Research Sponsored by the U. S. Department of Energy and performed at Oak Ridge National Laboratory, managed by Lockheed Martin Energy Research Corporation for the U. S. Department of Energy under contract No. DE-AC05-96OR22464. active region. This requires the PC front-end electronics be mounted within the PC detector’s active region. A minimum density packaging scheme is applied to the entire front-end electronics. In the following section, PC front-end electronics architecture is described. Following this architectural description, TGLD requirements, design and testing is given. II. PC FRONT-END ELECTRONICS ARCHITECTURE A typical PC front-end electronic channel consists of a charge sensitive preamplifier, signal differentiator, leading edge discriminator, beam crossing sampler and delay memory unit (DMU). The DMU delays and holds the pixel state until the PHENIX trigger system signals for event readout. A PC TGLD channel block diagram is shown in Figure 1. In addition to these TGLD operational functions, on-chip control and testing functions are included to allow remote control and evaluation of front-end electronics operational status while sealed inside the experiment after installation. Test Pulser Q in CSA ∆V LED current switch Vtest Vcomp DAC Reset I_threshDAC Select/ Disable one shot I out Figure 1. Single Channel Block Diagram of PC TGLD Three bare die TGLD, one DMU and three RS-485 interface chips are mounted chip-on board to form a 48 channel readout card (ROC). Figure 2 illustrates a PC ROC. Each PC detector subpanel has 45 ROCs arranged as five rows with nine ROCs each, for 2160 channels of pad readout. These 2160 channels of pad readout are controlled by a front- end module that interfaces with the PHENIX on-line data acquisition system.