J. Shanghai Jiaotong Univ. (Sci.), 2011, 16(6): 708-712 DOI: 10.1007/s12204-011-1138-z Efficient Clustering and Simulated Annealing Approach for Circuit Partitioning SANDEEP Singh Gill 1∗ , RAJEEVAN Chandel 2 , ASHWANI Kumar Chandel 2 (1. Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College, Ludhiana 141001, India; 2. National Institute of Technology, Hamirpur 177005, India) © Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg 2011 Abstract: Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper. The method converges asymptotically and probabilistically to global optimization. The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized. The proposed method begins with an innovative clustering technique to obtain a good initial solution. Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature. Key words: cut size, non polynomial hard, partitioning, simulated annealing, interconnections, very large scale integration (VLSI) design CLC number: TN 401 Document code: A 0 Introduction With the advances in very large scale integration (VLSI) technology the chip complexity is increasing, leading to more integration and increased design sizes. This leads to major chip estate being occupied by inter- connects, and leads to increased delay. Thus, improved physical design tools are necessary to handle such is- sues. Circuit net list partitioning is an important step in the VLSI physical design and involves the division of a circuit into smaller parts for ease of design and lay- out. The main objectives of circuit net list partitioning include minimization of number of interconnections be- tween the partitions and minimization of delay due to interconnections between partitions and ratio-cut min- imization. Multiple partitions can be obtained by re- cursively applying the method on the obtained bipar- titions. Recursive bipartitioning has been rated better than direct multiway partitioning [1] . Recursive biparti- tioning involves applying partitions on the obtained bi- partition successively until the number of the required partitions is obtained. Some easily applied algorithms for optimal clustering to minimize delay in digital networks were developed by Lawler et al [2] . Kernighan and Lin [3] proposed a heuris- tic for two-way partitioning which was the first itera- tive algorithm based on swapping of vertices. A more practical model based on hyper graphs was proposed, Received date: 2010-03-15 ∗E-mail: sandeepgill27@yahoo.in but was inefficient due to time complexity [4] . A new data structure bucket list for cell gains and proposed cell move with better time complexity was proposed [5] . Krishnamurthy [6] modified the work of Fiduccia and Matheyses [5] to introduce the concept of look ahead to choose the cell move. Various multiway partition- ing algorithms were proposed by modifying the algo- rithm of Fiduccia and Matheyses and Krishnamurthy and developing the appropriate data structures [7] , top down clustering and iterative primal-dual approach [8] , the dual intersection graph representation and ratio cut metric [9] . Areibi and Vannelli [10] described the appli- cation of Tabu search heuristic to circuit partitioning problem. Shahookar and Mazumder [11] proposed a genetic al- gorithm (GA) based evolutionary approach for circuit partitioning giving a significant improvement in result quality. A new hyper-graph partitioning algorithm hMetis is proposed, giving fast and better cutsize [12] . Areibi [13] discussed the implementation issues for ap- plying memetic algorithm for VLSI physical design. A multi-objective, hMetis partitioning for simultaneous cut size and circuit delay minimization is proposed [14] . Various algorithms using different optimization tech- niques are developed for system on chip (SoC) and hardware software partitioning [15-16] . Kolar et al. [17] have developed an algorithm for two way partitioning of a circuit, represented as a graph, using simulated an- nealing procedure, giving good results. Ghafari et al. [18] focused on minimizing the dynamic and sub threshold