ISSN: 2277-3754 ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 6, December 2012 229 High Speed Low Power Network Processors: Efficient Power Management Techniques Roopa Kulkarni, Dr. S. Y. Kulkarni Department of Electronics and Communication Engg. Gogte Institute of Technology, Belgaum Principal, M.S. Ramaih Institute of Technology, Bangalore Abstract: Power consumption is the bottleneck in achieving high performance. Power dissipation needs to be looked into the various levels of the design namely: circuit level, device level, architecture level and system level. With the increase in the networking, network processors (NP) have emerged as platform providing high performance and flexible in building the routers. Its observed from the survey of previous work, the processing elements, the micro engines (ME) of the NP consumes the power more. The simulation tool for this analysis used is the NepSim. Hence, the effort is to be made in reducing the power of the MEs. This paper initially briefs on the basics of power consumption in VLSI systems and the architecture of NP IXP1200. The emphasis is done on the analysis of power dissipated/consumed at the different levels of NP namely: packet level, instruction level and the architecture level. The later part of the paper wholly concentrates on the power management techniques at the architectural level. These different techniques are: clock gating, dynamic voltage and frequency scaling, power gating and very new method of designing the architecture in an asynchronous way. Index Terms: Network Processors, Low Power, Power Gating, Clock Gating, DVFS, Asynchronous Architecture. I. INTRODUCTION Network processors are the basic building blocks of today’s high-speed, high demand, quality-oriented communication networks. Designing and implementing network processors requires a new programming paradigm and an in-depth understanding of network processing requirements. Network processors (NPs) are chips—programmable devices that can process network packets (up to hundreds of millions of them per second), at wire-speeds of multi-Gbps. Their ability to perform complex and flexible processing on each packet, as well as the fact that they can be programmed and reprogrammed as required; make them a perfect and easy solution for network systems vendors developing packet processing equipment. Network systems, therefore, face an ever-increasing magnitude of packets they have to handle, while at the same time, the processing of these packets becomes more and more complex. This creates a gigantic performance problem. In order to cope with it, the traditional general purpose Central Processing Unit (CPU) in the network systems is replaced with Application Specific Integrated Circuits (ASICs), which are hardwired processing devices. However, the rapid changes in technology, dynamic customer requirements, and a pressure for time-to-market, short developing cycles and lots of revisions have become necessary. All of this has required an innovative approach toward network systems architecture and components. In today’s world, the need and the demand on high performance devices has increased exponentially. This increase has initiated driving more functionality and hence, a large no of transistors on a single chip. Hence, power consumption has become the bottle neck in achieving high performance, small size devices. This leads towards the research into low power, high speed VLSI systems. Power consumption is determined by the factors namely the [1] dynamic power, short circuit power and leakage power including the frequency, supply voltage, switching activity and capacitor. The power consumption equation is given as: P = P dynamic + P shortcircuit + P leakage (1) Dynamic power is also the switching power defined as: P dynamic = α * C * V 2 f (2) In equation 2, α is the switching activity, C the capacitor, V the supply voltage and f the frequency. This power can be lowered by using multiple Vdd or dynamic Vdd control. The switching activity can be reduces using the techniques of logic optimization, gated clock and prevention of glitches. To a larger extend the frequency is not increased but the same frequency is utilized efficiently at the logic and architectural level by employing the parallel processing obtaining the same throughput at lower clock frequency. P shortcircuit is the short circuit power caused by the rise and fall time of the input signal, which results in pull up and pull down networks to be ON simultaneously for a short moment. This power is the product of the short circuit current and the supply voltage. The leakage power consumption has increased with the aggressive scaling of the devices. This power is almost 30-40% of the total power consumption. The increase in the performance which means adding more functionality on a single chip gives rise to issues namely: power and thermal management, testing, memory bandwidth, fault tolerance, OS design, programming model, modeling and benchmark. Thus the research challenges are low power chip design, low power communication as communication consumes almost 35% of the power, platform development, testing and reliability and security. This paper aims at presenting the high performance network processor IXP 2XXX of Intel highlighting on what are power consumption, analysis and management concerns for the Network Processor. In this paper first, the overview of the network processor is described in section II. Focus will then be on the power