IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 11, NOVEMBER 2000 2153 Embedded HIMOS ® Flash Memory in 0.35 m and 0.25 m CMOS Technologies Dirk Wellekens, Jan Van Houdt, Member, IEEE, Luc Haspeslagh, Jorgo Tsouhlarakis, Paul Hendrickx, Ludo Deferm, and Herman E. Maes, Fellow, IEEE Abstract—In this paper, the performance and reliability charac- teristics of the 0.35 m/0.25 m High Injection MOS (HIMOS ® ) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler–Nord- heim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 m CMOS tech- nology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS ® cell exhibits a high degree of flexibility and scalability. A fast programming oper- ation (10 s) at 3.3 V supply voltage is combined with an endurance of well over 100 000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125 C. Furthermore, the cell has been scaled to a 0.25 m ver- sion, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V. Index Terms—Flash EEPROM memory, source-side injection. I. INTRODUCTION S INCE its introduction some ten years ago, flash memory has experienced a continuous growth due to its unique com- bination of fast programming capability, electrical erasability, and high density. These features have given flash technology the potential to become the technology of choice for new huge- volume applications. The ever-increasing densities imposed by this evolution are mainly provided by scaling of the transistor di- mensions, which also makes supply voltage scaling mandatory. Since drain voltage scaling is known to substantially degrade the programming speed offered by conventional channel hot-elec- tron injection, source side injection (SSI) has become a com- petitive alternative for flash programming [1], [2]. Moreover, because this mechanism combines moderate voltages with low power consumption, it has yielded the most promising cell struc- tures so far, including the High Injection MOS (HIMOS ® ) de- vice [2]–[4]. Unlike most embedded flash technologies, which still use rather complicated processing schemes with a large number of nonstandard steps only available from stand-alone memory technology, the HIMOS ® cell requires only four masks Manuscript received January 3, 2000. The review of this paper was arranged by Editor G. Baccarani. D. Wellekens, J. Van Houdt, L. Haspeslagh, J. Tsouhlarakis, P. Hendrickx, and L. Deferm are with Interuniversity Micro-Electronics Center, B-3001 Leuven, Belgium (e-mail: Dirk.Wellekens@imec.be). H. E. Maes is with Interuniversity Micro-Electronics Center,, B-3001 Leuven, Belgium, and Katholieke Universiteit, Leuven, ESAT-INSYS, B-3001 Heverlee, Belgium. Publisher Item Identifier S 0018-9383(00)09624-6. on top of digital CMOS. The cell combines SSI programming with drain erase and proves to be a robust, well-scalable, low- voltage and low-cost flash concept. In this paper the 0.35 m HIMOS ® cell technology is pre- sented, showing high programming performance even as the drain voltage is scaled to 3.3 V, while maintaining excellent re- liability margins in terms of endurance, sensitivity to disturb ef- fects and retention. The characteristics are extensively analyzed on typical cells and extended to 1 Mbit memory circuits that have been designed to demonstrate the 0.35 m technology. Fur- thermore, the 0.25 m HIMOS ® technology is explored, paying attention to a new promising mechanism for programming. II. DEVICE DESCRIPTION The HIMOS ® concept uses a split-gate transistor, consisting of a floating gate channel in series with a control gate channel (Fig. 1), in order to reconcile the conditions for a high hot-elec- tron generation rate and a high electron collection efficiency [5]. This results in a very efficient programming operation at the source-side of the floating gate channel. The HIMOS ® cell makes use of this very efficient source-side injection (SSI) pro- gramming mechanism through the incorporation of a third gate (program gate, PG), located on the field oxide region, in order to couple a moderate voltage onto the floating gate (FG). The gate at the source side of the channel (control gate, CG) acts as the gate of the injection transistor, and at the same time as a select transistor to prevent overerasure. In the 0.35 m HIMOS ® technology, the 7 nm CMOS gate oxide also serves as the tunnel oxide of the memory transistor. An 8-nm oxide is grown under the control gate together with the interpoly oxide, which results in a 15-nm polyoxide between the first and second poly layer. This scheme minimizes the number of steps and the CMOS parameter shifts resulting from the in- troduction of the flash module. For the cell, only two masks are added to plain CMOS (the second poly and the erase junction), whereas the high-voltage (HV) circuitry requires two more (a 15 nm HV oxide and a HV n-well to handle negative voltages without requiring a triple well process). This limits the number of additional masks to only four. Although the split-gate struc- ture with a third (program) gate results in a rather conservative cell area of 3.25 m , it gives much more flexibility and a much better scalability in return. Not only can the FG and CG channel lengths be scaled to the minimum feature size, but their respec- tive gate oxides can be scaled independently of one another as well. In this way, the CG transistor can be further scaled ac- cording to the CMOS scaling rules to maintain the high read-out 0018–9383/00$10.00 © 2000 IEEE