Low power VLSI architecture design of BMC, BPSC and PC schemes G. Rajakumar 1 • A. Andrew Roobert 2 • T. S. Arun Samuel 3 • D. Gracia Nirmala Rani 2 Received: 25 April 2017 / Revised: 29 June 2017 / Accepted: 14 July 2017 Ó Springer Science+Business Media, LLC 2017 Abstract Line coding is used to tune the wave form based on the properties of the physical channel. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. The first objective of the proposed work is to design Generation and Degeneration operations of BMC, BPSC and PC tech- niques in a single chip. The second objective is to reduce the area and power consumption, by modifying the number of MOS devices used to design the system and by adjusting the width of the MOS devices. The proposed system is designed with 59 transistors and simulated using Cadence Ò 90 nm technology. This occupies 1290 lm 2 . Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data has equal possibility of high and low level signals, PC tech- nique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable. Keywords VLSI design  Low power  Line coding  BMC  BPSC  PC 1 Introduction Communication system requires source coding for data compression, channel coding for error correction, crypto- graphic coding for data security, and line coding to opti- mize the signal. This work concentrates on the hardware design of line coding techniques. BMC or FM1 coding, BPSC or FM0 coding, Miller coding, and PC or Manch- ester coding are used as major line coding techniques. Manchester code generator runs at 1 GHz and uses 32 transistors for a single operation [1]. The systems designed for Manchester/Miller encoder and Manchester/FM0 encoder have no discussion about the decoder part [2–7]. BMC also can be combined in the system designed for BPSC/PC generator and degenerator [8] as shown in the proposed work. Based on the application and properties of the digital system, the possibility of 1’s and 0’s present in the output signal will vary. As an example, during a voice call, user from one end will be talking (more number of 1’s) and from another side will be idle (more number of 0’s). Based on this, BPSC or BMC or PC have been used to reduce transitions and thereby reduces power consumption [9, 10]. BMC is used in AES3 (Audio Engineering Society), S/PDIF (Sony/Philips Interface Format), Magnetic Stripe cards, Single density Floppy disks and SMPTE time code (Society of Motion Picture and Television Engineers). PC is used in Ethernet over twisted pair technology & T. S. Arun Samuel arunsamuelece@nec.edu.in G. Rajakumar gmanly12@gmail.com A. Andrew Roobert andrewroobert@gmail.com D. Gracia Nirmala Rani gracia@tce.edu 1 Department of Electronics and Communication Engineering, Francis Xavier Engineering College, Tirunelveli, India 2 Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai, India 3 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, India 123 Analog Integr Circ Sig Process DOI 10.1007/s10470-017-1025-0