Capacitor Multiplier with One Transconductor Cell Paul Coste*, Paul Martari*, Marius Neag*, Vlad Ionescu** *Technical University of Cluj-Napoca, Basis of Electronics Department, 400027, Romania *E-mail: coste.paul@bel.utcluj.ro, paul.martari@bel.utcluj.ro ** Infineon Technologies Romania ** E-mail: vlad.ionescu@infineon.com Abstract—A new programmable capacitance multiplier implementation is presented in this paper. It is based on a fairly known architecture, but the proposed circuit employs only one linear transconductor (Gm cell). The mathematical analysis of the new capacitance multiplier is presented along with simulations performed on a circuit implemented in standard 0.18-μm CMOS process. Two applications are also presented: a triangular waveform generator and a fully differential lossy integrator, both with emulated capacitances programmable over three octaves. Keywords— capacitor multiplier, current mode, transconductor, analog integrated circuits 1. Introduction In general, the integration of capacitances larger than hundreds of picofarads is not feasible/desired in general-purpose integrated technologies, due to the large die area they require. Using external capacitors is not always acceptable, as this implies dedicated pins and obviously increases the bill-of- materials (BoM) for the application. Another option is the implementation of a circuit that emulates the features of a large capacitance while actually employing a placed/integrated capacitor many times smaller than the emulated value – that is, a capacitance multiplier. In this case, it is often required to provide means for adjusting or programming the capacitance gain factor (G), at least in order to compensate for variations of the process, supply voltage and temperature (PVT). Several circuit solutions for implementing capacitance multipliers have been reported in the open literature. Most of them are based on the Miller effect; thus, they can be classified as a voltage mode approaches. Their performance is usually hindered by signal swing limitations since the maximum voltage applied to the capacitance is reduced by the gain factor, G. Current mode approaches are faster and have a wider dynamic range [1]. The principle of current mode approach is I B +ic I B C Zequivalen t KI B +(K+1)ic K(I B +ic) V DD 1:K M1 M2 Fig. 1 Current mode approach for capacitor multiplier. shown in Fig. 1. It is based on a simple current mirror, which senses the current passing through the placed capacitor (C) and scales it by the current gain, K. This way, the equivalent capacitance is seen at the output of the current mirror appears G=(K + 1) larger than C. However, most circuits reported in literature provide a very low-quality factor, Q, for the resulting multiplied capacitance, mainly due to the relatively large input resistance of the current mirror, Rin = 1/gm [2]. Other current mode implementations use second-generation current conveyors as active devices to multiply the capacitance but they do not allow a variable capacitance multiplication factor [3]. A typical solution for a capacitor multiplier is the circuit presented in [4]. The circuit presented in Fig. 2 a), uses two transconductance amplifiers (OTAs) with transconductance gains gm1 and gm2. The transconductance of OTA2 ca be adjusted by means of a control voltage or a bias current. One terminal of capacitor C is connected to OTA1. OTA1 uses unity gain negative feedback and operates as a low-value series resistor R1=1/Gm1 connected between the remaining capacitor terminal and ground. The equivalent circuit with its series resistor R1 is presented in Fig. 2 b). For a purely capacitive behavior (Q=∞) the value of R1 should be zero. In order to achieve a high Q, OTA1 should have a large gm while OTA2 should have a large output resistance.