Design And Implementation Of Sharc Processor T. Chandrasekhar Associate Professor Ciet Engineering College, Rajahmundry (Ap). J. Suneel Chakravarthi Assistant Professor Ciet Engineering College, Rajahmundry (Ap). ABSTRACT This paper deals with the design and implementation of the 32-bit floating point Digital signal processor with MIPS (microcomputer with out interlocked pipeline stages).The designed DSP has 32 floating point MIPS instructions, instruction sets suitable for processing digital signals and consists of super Harvard architecture, 40-bit ALU, 5 level pipelines, 17-bit X 17-bit parallel multiplier for single-cycle MAC operation, 8 addressing modes, 8 auxiliary registers, 2 auxiliary register arithmetic units, two 40-bit accumulators and 2 address generators. The VHSIC HDL coded synthesizable RTL code of the DSP core has a complexity of 80,670 in the two input NAND gates. We verified the functions of the DSP by a simulation with a single instruction test as the first step and then implemented the DSP with the FPGA. The test vectors have a single instruction test, combination of single instructions and algorithm applications, ADPCM vocoder and the MP3 decoder. After FPGA verification, the DSP core carried out three test vector sets which are tested at FPGA at the 106 MHz clock rates. General Terms Digital signal processor that can execute millions of instructions per second Keywords: VLSI, DSP, MIPS, FPGA 1. INTRODUCTION As per the growing technology, the size of processor is smaller and so many portable devices are manufactured. Digital Signal Processing is distinguished from other areas in computer science by the unique type of data it uses signals. In most cases, these signals originate as sensory data from the real world: seismic vibrations, visual images, sound waves, etc. DSP is the mathematics, the algorithms, and the techniques used to manipulate these signals after they have been converted into a digital form. This includes a wide variety of goals, such as: enhancement of visual images, recognition and generation of speech, compression of data for storage and transmission, etc. Therefore the importance of the DSP (digital signal processor) which can process fast and accurate digital signals for audio/image processing or data communication has been getting bigger. This paper includes information of the design and implementation of the DSP core on FPGA. The suggesting DSP has advanced Harvard architecture (SHARC) and instruction sets suitable for processing digital signals and MIPS instruction sets. Comparing with fixed point, floating point dsp provides high range, precision and accuracy. But it suffers from the problem of speed reduction for DSP computations. In order to compensate this speed reduction problem, MIPS has introduced in the DSP, in this paper. 2. DESIGN The suggesting DSP has a couple of features of architecture because DSP has to carry out many digital signal algorithms at a real time. First, DSP has fast and optimized multiplier for operating the MAC instruction during one cycle. And it has the advanced Harvard architecture called super Harvard architecture to improve an operating speed. For a movement of bust bits used frequently in digital signal algorithms. The overall architecture of the suggesting DSP consists of data and address buses, a central processing unit, a control unit and memory interface unit[3], shown in Figure 1. Figure 1. Typical DSP architecture Figure 1, presents a more detailed view of the DSP architecture, showing the I/O controller connected to data memory. This is how the signals enter and exit the system. For instance, the DSP’s provides both serial and parallel communications ports. These are extremely high speed connections. For example, at a 40 MHz clock speed, there are two serial ports that operate at 40 Mbits/second each, while six parallel ports each provide a 40 Mbytes/second data transfer. When all six parallel ports are used together, the data transfer rate is an incredible 240 Mbytes/second. 1689 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 www.ijert.org Vol. 2 Issue 6, June - 2013 IJERTV2IS60713