Advanced Research in Electrical and Electronic Engineering p-ISSN: 2349-5804; e-ISSN: 2349-5812 Volume 3, Issue 5, October-December, 2016, pp. 369-374 © Krishi Sanskriti Publications http://www.krishisanskriti.org/Publication.html A Method for Improving the Settling Time of Phase-locked loop during Acquisition for Communication Systems Geetamoni Konwar 1 , Munmee Borah 2 and Tulshi Bezboruah 3 1,2,3 Department of Electronics & Communication Technology Gauhati University Guwahati, India E-mail: 1 geetak222@gmail.com, 2 munmeeborah01@gmail.com, 3 zbt_gu@yahoo.co.in Abstract—This paper describes a novel method for proportional- integral-derivative controlled phase-locked loop model for communication system for better settling time during acquisition. A proportional-integral-derivative controlled block is inserted in place of a 4 th order loop filter of the phase-locked loop. The s-domain transfer function of the system is derived for linear analysis. The settling, phase margin, bandwidth and stability of the system are analyzed through behavioral simulation by using MATLAB platform. It is observed that the proportional-integral-derivative controlled phase-locked loop model reduces the settling time (~ nS) in comparison to phase-locked loop with 4 th order loop filter in the loop (~μS). Keywords: Phase Margin, PID controller, PLL, Loop filter, settling time. 1. INTRODUCTION The history of the phase-locked loop (PLL) dates back to as early as 1932 by Henri de Bellescize, when British researchers developed an alternative to Edwin Armstrong's super heterodyne receiver, the Homodyne or direct-conversion receiver. In 1970, it became widespread because of the development of integrated circuits (ICs) [1, 13, 14]. The PLL is a very interesting and useful building block available as single integrated circuits in modern communication system design. The PLL is a feedback control system that generates an output signal having a frequency which is synchronized to that of an input reference signal [2, 3, 13, 14]. As shown in Fig.1, PLL consists of the four blocks namely: (a) phase detector (PD), (b) loop filter (LF), (c) voltage-controlled oscillator (VCO), and (d) a divide-by-N counter. The PD is a type of multiplier whose output consists of a dc voltage which has the phase information of the input signal. The phase error between the input and output signal is fed to the LF which integrates the signal to smoothen it. The LF output is given to the VCO input. The VCO generates an output signal with a frequency which is proportional to the input voltage. The PLL is considered to be phase locked when Fig. 1: Block diagram of PLL the loop phase error is constant and the loop is in stable equilibrium state [2, 14, 15]. PLL are widely employed in radio, computers, telecommunications, satellite communication, airborne navigational systems, frequency modulation and other electronic applications. Frequency synthesis is currently a very important PLL application area. The settling time of PLL plays a significant role in applications which need fast frequency switching as frequency hopping spread spectrum (FHSS) communication system, step frequency radars (SFR) and wireless local area networks (WLANs) [5,6,10,16]. Also, frequency modulated (FM) transceiver application requires carrier frequency and local oscillation frequency with low settling time. Thus, it is necessary to improve the settling time of PLL without effecting the noise performance and power consumption of the system [10]. In this paper we discuss a method to minimize the settling time of PLL system for communication system. 2. REVIEW OF RELATED WORKS In 2010, K. Kalita, J. Handique, T. Bezboruah and K. Bora described a model for the analysis and software implementation of proportional-integral-derivative (PID) controlled higher order PLL to reduce the settling time up to 76.79%, 54.70% and 43.54% for 2 nd , 3 rd and 4 th order PLL respectively [7].