IEEE TRANSACTIONS ON COMPUTERS, VOL. 47, NO. 9, SEPTEMBER 1998 971 Using Decision Diagrams to Design ULMs for FPGAs Zeljko Zilic and Zvonko G. Vranesic Abstract—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; in this paper, we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits. Index Terms—FPGAs, ULMs, BDDs, classification of logic functions, synthesis of logic functions. ——————————F—————————— 1 INTRODUCTION HE first commercially available Field-Programmable Gate Arrays (FPGAs) in 1985 had an array of three- input logic blocks, where each block could realize any function of three variables using an 8-bit RAM. Such a block is a lookup-table with three inputs (LUT.3). A decade or two before that, there was a significant amount of theo- retical research on Universal Logic Modules (ULMs) [7], [17], [21], which are logic blocks capable of realizing all functions of a fixed number of variables assuming that permutations and negations of variables are provided out- side these blocks. Some of the established FPGA families from Actel, Xilinx, and Pilkington use blocks derived from such a concept of ULMs. However, more systematic re- search on the use of ULM circuits as logic blocks in FPGAs appeared only recently [15], [23], [24], [16]. In this paper, we propose a new type of ULMs for use in SRAM-based FPGAs. Practical designs for three- and four-input LUT (LUT.3 and LUT.4) replacements are presented, together with the methodology to systematically derive such blocks. ULMs are traditionally defined as blocks with m general purpose inputs that can realize any function of up to n in- puts, n < m, under the assumption that permutations and negations of signals are generated cost-free outside the logic block [21]. While the inversions are, in general, not free in FPGAs, as will be shown in Section 5, the permuta- tions of inputs are free for some routing architectures: In Altera’s 8k and 10k series FPGAs [2], all possible input sig- nals can be connected to all the input pins of a logic block. Such architectures with fully connected inputs are considered in [5] for routing structures in hierarchical FPGAs [1]. The ULM blocks achieve their functionality by bridging some inputs and/or assigning them to a constant; these are as- sumed to be costless operations. This concept is illustrated in Fig. 1a. Classical ULM research was based on this defini- tion of ULMs. Lower and upper bounds are known for m as a function of n, and they asymptotically approach each other. To realize all n-input functions, the total number of inputs m needed is on the order of 2 n /log(n). Several meth- ods have been proposed for constructing such ULMs [7], [17], [21]. Recent research on ULMs has been focused on investi- gating the trade-off between the functionality of logic blocks and their usefulness in real applications. The re- search presented in [15] and [23] attempted to find a subset of functions that a ULM can realize so that it behaves as close as possible to the LUT. These papers deal with blocks that have functionality comparable to LUT.3 [15] and LUT.4 [23], but they are not functionally complete. 1 The block in [15] has four inputs and realizes 10 out of 14 nonequivalent three-input functions, while the block in [23] requires eight inputs to realize almost all four-input functions. In this paper, we propose a more practical type of ULMs. It is known that adding pins to logic blocks in realistic FPGAs is very costly [18]. Since a total of m = O(2 n /log(n)) inputs are needed for realization of an n input function in a standard ULM, an unreasonable amount of routing re- sources may be needed if such blocks are used. 2 In addition to providing the access to all m input pins, the routing net- work must provide resources for bridging the input pins. There are O(m 2 ) bridging connections possible for each block. These are the reasons why, in [15], the total number of inputs is limited to four, as opposed to eight as in [23]. We propose a class of ULM circuits that avoids this problem and limits the number of input pins to n by using separate 1. The block in [15] is named “semi-ULM” to express the fact that it is not functionally complete. 2. It was noticed early [21] that the standard ULMs are not very practical because of the large number of input pins needed. 0018-9340/98/$10.00 © 1998 IEEE ²²²²²²²²²²²²²²²² • Z. Zilic is with the Department of Electrical and Computer Engineering, McGill University, McConnell Engineering Building, 3480 University Street, Montreal, Quebec, Canada H3A 2A7. • Z.G. Vranesic is with the Department of Electrical and Computer Engi- neering, University of Toronto, 10 King’s College Road, Toronto, Ontario, Canada M5S 3G4. E-mail: {zeljko, zvonko}@eecg.toronto.edu. Manuscript received 17 Mar. 1997. For information on obtaining reprints of this article, please send e-mail to: tc@computer.org, and reference IEEECS Log Number 104677. T