Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits Ambika Prasad Shah a , Santosh Kumar Vishvakarma a,* , Sorin Cotofana b a Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, M.P. 453552, India b Department of Computer Engineering, Delft University of Technology, Delft 2628, the Netherlands ARTICLE INFO Keywords: Schmitt trigger NBTI Threshold voltage degradation Reliability Design for reliability ISCAS’89 s27 benchmark suite ABSTRACT Negative Bias Temperature Instability (NBTI) in PMOS transistors results in increased transistor threshold vol- tage, is considered the major contributor to circuit performance degradation and to alleviate its effect appro- priate design and lifetime measures are required. In this paper, we concentrate on a design-time solution, i.e., the replacement of CMOS inverters by more reliable counterparts, i.e., Schmitt Trigger (ST) and NMOS only Schmitt Trigger with Voltage Booster (NST-VB). We first compare the three candidates implemented in 32 nm CMOS technology concerning delay variation. Our results indicate that, after three years of NBTI stress, NST-VB ex- hibits an almost negligible delay shift of 0.47%, while ST and CMOS inverter experience a delay shift of 7.2% and 5.32%, respectively. Subsequently, we extend the scope and assume the ISCAS’89 s27 circuit as a discussion vehicle. Our evaluations indicate that after 3-year stress time, the critical path delay of the s27 CMOS, ST, and NST-VB based implementations increases by 105.1 ps, 185.2 ps, and 94.2 ps, respectively. To put things into a better perspective, we introduce the Inverse Power Area Reliability Product (IPARP) as compound reliability metric. Our analysis indicates that the normalized IPARP values for ST and NST-VB implementations are 0.062 and 1.903, respectively, compared to CMOS implementation. 1. Introduction Lifetime reliability grew to be of the biggest design challenges with the continuous transistor dimensions scaling for high performance and energy-efficient digital circuits, e.g., microprocessors [1]. Time-de- pendent aging mechanisms such as Bias Temperature Instability (BTI), Time-Dependent Dielectric Breakdown (TDDB), and Hot Carrier Injec- tion (HCI), significantly degrade circuits performance during their op- eration [2,3]. BTI is due to Si/SiO 2 interface dangling bond defects that allow for charge trapping within the interface even at small energy, which results in threshold voltage (V th ) increase and affects both NMOS and PMOS devices [4]. In particular, Negative Bias Temperature In- stability (NBTI) is the dominant aging phenomenon in digital circuits, which majorly effects the PMOS transistors at elevated temperature (125 °C). Whereas PBTI is no longer negligible if the high-k dielectric is used. NBTI increases the threshold voltage [5], reduces the carrier mobility, and hence significantly increases the delay of CMOS gates and circuits [6,7]. The threshold voltage shift, and by implication due to NBTI aging-induced CMOS circuit delay augmentation, tends to be more pronounced as technology scales down [8,9]. As a matter of fact a threshold voltage increase of about per technology scaling step 4% has been reported in [10] and [11], e.g., ∼38% for 65 nm and ∼42% for 45 nm after a stress time of 10 5 s. This clearly indicates that with feature size shrinking NBTI related progressive lifetime degradations came to be more severe and ensuring lifetime reliability became an impossible mission without the introduction and utilization of proper design techniques. 1.1. Effect of NBTI on CMOS circuits Fig. 1 presents the NBTI induced threshold voltage shift (ΔV th ) ex- perienced by a 32 nm technology PMOS transistor at elevated tem- perature and under different stress conditions, i.e., duty cycle (β) and stress time using HSPICE simulation [13]. One can observe in the figure that: (i) most of the degradation occurs in the first year, reaching 50 to 70 mV, depending on the duty cycle, after which V th continues to change but at a significant lower pace and (ii) the input duty cycle determines the threshold voltage shift magnitude and circuits under low duty cycle suffer less from NBTI detrimental effects. NBTI stress is an aggravating factor for CMOS inverter susceptibility to latch-up during slow H-L and L-H transitions [14]. The straightfor- ward solution to overcome NBTI induced latch-up is the utilization of https://doi.org/10.1016/j.microrel.2019.06.083 Received 15 October 2018; Received in revised form 29 May 2019; Accepted 28 June 2019 * Corresponding author. E-mail addresses: ambika_shah@rediffmail.com (A.P. Shah), skvishvakarma@iiti.ac.in (S.K. Vishvakarma), s.d.cotofana@tudelft.nl (S. Cotofana). Microelectronics Reliability 102 (2019) 113391 0026-2714/ © 2019 Elsevier Ltd. All rights reserved. T