A CMOS integrated opto-electronic receiver for automotive applications using 1 mm POF J. Put, 1 , J. Bauwelinck, 1 X. Yin, 1 X.-Z.. Qiu, 1 J. Vandewege, 1 O. Chasles, 2 A. Devos, 2 and P. De Pauw 2 1 Ghent University, IMEC/INTEC, Sint-Pietersnieuwstraat 41, 9000 Gent, Belgium. 2 Melexis, Rozendaalstraat 12, 8900 Ieper, Belgium. This paper presents the design and measurements of a fully integrated opto-electronic receiver operating at 650 nm, suitable for automotive POF data communication networks. The cost is minimized by applying butt coupling and integrating the PIN photodiode and the transimpedance amplifier in a 0.35 μm CMOS technology with a modified epitaxial layer. To cope with the large capacitance of the 1 mm photodiode and to improve the receiver’s sensitivity, a fully differential structure with a dummy photodiode and regulated cascode buffer is proposed. Measurements show a sensitivity of -22.3 dBm at a BER of 10 -9 for a stress MOST-pattern at a line rate of 334 Mb/s. Introduction Plastic optical fibers gain a lot of interest for automotive data communication networks as they offer many advantages, such as the insensitivity to electromagnetic interference, the relatively high bandwidth, the ease of handing and installation, low weight and a small cross section. The design of network components for automotive data communication is very challenging as it requires a high performance at very low cost in an automotive environment, which is characterized by a high temperature range (junction temperatures of -40 °C to 125 °C) and a large level of electromagnetic interference [1]. This paper presents a low-cost receiver with large-area photodiodes integrated in a CMOS process using a modified wafer with a 20 μm intrinsic layer. The large junction capacitance of 5 pF (+/- 25 %) complicates the receiver’s design as it reduces the achievable bandwidth and sensitivity severely. Design of the differential opto-electronic integrated receiver Figure 1(a) depicts a simple block diagram of the realized receiver chip, existing of two identical integrated photodiodes, a differential current buffer (CB), a differential Tran- simpedance Amplifier (TIA) and an output buffer. A dummy photodiode, which is fully shielded from any incoming light, represents the parasitic PIN capacitance, in order to make the receiver as symmetric as possible. In this way, the receiver is immune to com- mon mode noise, e.g. originating from the substrate and electromagnetic interference. Highly sensitive front-illuminated NIP photodiodes, with a relatively small junction ca- pacitance, are realized in 0.35 μm CMOS as follows (Figure 1(b)): a 20 μm thick, very low doped epitaxial layer is applied to the p+ substrate wafer, acting as the intrinsic layer of the PIN structure. The majority of the light passes the very low resistance cathode, realized by a thin, but very high n+ implementation at the top of the wafer. The p+ sub- strate is acting as a common anode, which is connected at the top of the wafer by means