Application of Fault Simulation Techniques to Design Validation Quality Measurement Celia López 1 , celia @ing.uc3m.es Teresa Riesgo 2 , Yago Torroja 2 , Javier Uceda 2 , teresa, yago, uceda@upmdie.upm.es Luis Entrena 1 entrena @ing.uc3m.es 1 Universidad Carlos III de Madrid- EPS Grupo de Microelectrónica. Area de Tecnología Electrónica c/Butarque, 15. 28911. Madrid (Spain) 2 Universidad Politécnica de Madrid - ETSII División de Ingeniería Electrónica c/José Gutiérrez Abascal, 2. 28006. Madrid (Spain) Abstract Functional validation contributes to check the quality of designs. When applied in early steps of design cycle it will help to detect design errors. If functional validation is good enough, it will detect a large number of design errors. It is necessary to assure the quality of functional validation so a method to measure this quality has been proposed and developed, based on error modelling and simulation. Method automation is needed for making it more general and applicable. In the process of automation, special attention should be paid to error simulation, which implies the greatest amount of time employed. Fault simulation is a well-known problem that presents a set of optimum simulation techniques, which will help in the enhancement of error simulation performances. A selection of these techniques has been included in error simulation and some experiments have been developed in order to check the obtained benefits. 1. Introduction Integrated circuits are getting faster, lower power consuming, cheaper and smaller every year. Hard design requirements are imposed to designers to obtain good quality results. Several initiatives have been developed to help the design teams in the process of generating digital integrated circuits. Design process has been automated and now designers can apply their efforts to obtain better architectures and performances. This automation is very useful because reduces time and effort employed and raises the probability of success. On the other hand, this automation makes necessary to assure the quality of design in the first steps of the process, because all design errors will be propagated automatically through following steps till the final circuit. Therefore, special attention should be paid to quality from first stages in design process. This way, no bad surprises will appear at final steps of design, when re-design is very expensive. Functional validation, plays an important role in the quality of the design process because it is checking the functionality described in all design cycle steps, against specifications, and besides it helps to detect design errors. These design errors are mainly related to functionality and they are detected by applying a complete functional validation. The functionality is more explicit at higher level of abstractions, so it is easier to detect design errors in the first steps of design cycle. Hence, it is important to measure the quality of functional validation for design descriptions in early steps in design process. In this paper we present a method for measuring this quality, applicable to Register Transfer Level descriptions in VHDL. The method is based on error models that are applied to original design descriptions and that should be detected by the test bench under study. The quality measurement is calculated by means of error simulation that compares functionality of original design description and description with inserted errors. The error coverage (detected errors over inserted errors) is the quality measurement of the test bench under study. The proposed method has been automated in order to be included in design cycle. In the process of automation of the method, some studies have been developed in order to obtain good results in terms of system resources, execution time and disk space for computers to be used. Error simulation is the most critical task in the method application, especially with respect to execution time and disk space required. Fault simulation is a problem that has been deeply studied when dealing with manufacturing test. Taking into account the differences between both simulations, some techniques from fault simulation could be applied to error simulation in order to reduce system resources requirements (fault dropping, concurrent and parallel simulations, etc.). In this paper the adoption of some of these techniques from fault simulation, for the enhancement of error simulation, is detailed. Experimental results studying the adoption of these techniques will be exposed and analysed. Finally, some conclusions will be given. 2. Error Modelling Several authors have studied the problem of functional validation quality. Only a few of them have chosen VHDL language and RTL level for