Electron Mean-Free Path for CNT in Vertical Interconnects Approaches Cu Marleen H. van der Veen, a,1 Yohan Barbarin, a Yusaku Kashiwagi, b and Zsolt Tökei a a imec, Leuven, Belgium b Tokyo Electron Ltd., Tsukuba, Japan 1 email: vdveen@imec.be ABSTRACT A carbon nanotube (CNT) contact length scaling is used to derive the electron mean-free path (λ CNT ) after full integration. A CNT-to-metal contact resistance of 76 Ω and lower was obtained for 150 nm diameter contacts. By estimating the number of conducting walls in the CNT bundle, a λ CNT of 74 nm is found, which is longer than for Cu. We propose a more conservative approach of calculating λ CNT solely from electrical data. The result is that our CNT interconnects have ballistic transport over 24 nm, which is 5 times longer than reported so far. INTRODUCTION As the dimensions of the IC building blocks shrink to the nanoscale, the resistance and electrical resistivity of metals used in the interconnect technology [1] is a research topic of increasing interest. Electron scattering events arising from grain boundaries and surface roughness are becoming more critical. In this respect, carbon nanotubes (CNT) are one of the possible alternatives [2] to replace traditional metals at the nanoscale. [1] CNT offer a great advantage as native device interconnect due to their (i) high current capacity (> 10 3 MA/cm 2 ), (ii) ballistic transport up to µm-lengths, and (iii) a true bottom-up growth process which is a fill solution for sub-5 nm nodes. The key to realizing this is a fully integrated CNT interconnect using CMOS compatible processes. After integration, the CNT should fulfill the promises as set by theory and in ideal lab surrounding. [3–5] Reports show that integration challenges for CNT bundles in via holes remain significant [6–11] especially in terms of scaling the diameter and aspect ratio (AR) of the vias. The electrical performance of CNT interconnects is studied in order to understand its properties and to evaluate whether it has potential for future technology nodes. A 200-mm full- wafer level integration of CNT is adopted in vertical contacts of 150 nm in diameter (aspect ratio 2.4) and optimized by evaluating the electrical response upon process changes. In this paper the top metallization of the CNT with Cu or W is compared electrically in two length scaling series with 7 wafers. Furthermore, we demonstrate how the electron mean-free path λ CNT of individual CNT walls can be extracted from such length scaling series of fully integrated CNTs. This provides a detailed understanding of the performance of the CNT interconnects. Our approach uses a combination of electrical data (length scaling of the CNT contacts) and structural characterization (such as TEM) of the CNT. By comparing the λ CNT values for different length series, we show that the electron mean-free path was improved 5 times after optimizing the integration for CNTs. CNT CONTACT INTEGRATION AND LENGTH SCALING The cross-sectional SEM images in Fig. 1 show the length scaling of vertical CNT contacts with a W single damascene top metallization process. A schematic of the CMOS compatible integration steps used for these wafers is depicted in Fig. 2. The CNTs were grown in a remote microwave plasma enhanced CVD tool (15 min, 40/45/1000 sccm C 2 H 4 /H 2 /Ar, 3T, 1.5kW, 540ºC) [12] and encapsulated in 30 nm Al 2 O 3 (ALD of TMA/H 2 O at 150ºC). A layer of 65 nm SiO 2 by SACVD was used for the planarization (50 s oxide CMP) to remove growth residuals, [12] expose the CNT tips, and to control the CNT interconnect length by systematically increasing the CMP time for each wafer. The CNT interconnect length is taken as the height between the top and bottom metal (TiN to Ti/TiN distance in Fig. 1) as measured by SEM and averaged for a center and edge die. The length scaling methodology used in this study is detrimental to extract the λ CNT . Therefore, a uniformity analysis of the 50 s oxide CMP process was performed for 7 CNT wafers. The growth residuals are removed with the oxide slurry at a rate of 9±1 nm/sec. The within-wafer-non uniformity from center to edge was found to be less than 15% for most of the wafers (i.e., ~ 20 nm). The wafer-to- Fig. 1. XSEM showing the length scaling of 150 nm diameter CNT interconnects with Ti/TiN/W top metallization (3 wafers). 4 978-1-4799-5018-8/14/$31.00 ©2014 IEEE 181