High Performance Strained Si/SiGe N-channel MOSFETs: Impact of Alloy Composition and Layer Architecture SH Olsen, LS Driscoll, KSK Kwa, S Chattopadhay, AG O’Neill School of Electrical, Electronic and Computer Engineering, University of Newcastle, U.K. Phone: +44-(0)191-280-4310 E-mail: sarah.olsen@ncl.ac.uk Abstract Single and dual n-channel strained Si MOSFETs, fabricated by the same high thermal budget process, are compared for the first time. Si 1-x Ge x virtual substrates, having 0.1 < x < 0.3, are used to compare off-state and on-state device performance. Transconductances and current drive up to 240% higher than control Si MOSFETs are demonstrated. Electron mobility is found to peak using a virtual substrate composition of Si 0.75 Ge 0.25 . 1. Introduction Growth of strained Si on SiGe virtual substrates is known to improve carrier mobility and so increase MOSFET current and transconductance. Theoretical studies have suggested that the optimum performance of strained Si/SiGe MOSFETs is achieved by the use of a strained Si surface electron channel and a buried hole channel of compressively strained SiGe [1]. As virtual substrate Ge composition increases, strain relaxation during high temperature MOSFET processing may degrade overall device performance and it is unclear what impact Ge diffusion will have on device operation, particularly if a compressively strained SiGe channel of high Ge composition is used. 2. Device Design and Fabrication Strained Si n-channel MOSFETs were fabricated on relaxed Si 1-x Ge x virtual substrates (VS) with x = 0.10, 0.15, 0.20, 0.25 and 0.30. The rms surface roughness of the 20% VS was measured as 5 nm using AFM (Fig. 1) and CMP was not used to smooth the cross-hatching. SiGe alloy compositions on fully processed devices were confirmed by SIMS and electron dispersive spectroscopy. Dual channel architectures, comprising a compressively strained Si 0.7 Ge 0.3 layer grown between the strained Si surface channel and a Si 0.85 Ge 0.15 VS were also grown. Strained Si/SiGe device fabrication followed a conventional 0.25 μm CMOS process. A gate oxide was thermally grown at 800 °C, resulting in a 6 nm gate oxide. Polysilicon was deposited and devices down to 150 nm gate length were patterned using electron-beam lithography. As and P were implanted into the source, drain and gate and annealed at 1050 °C for 20 sec. Back-end processing comprised deposited silox and BPSG with Al metalisation. Control Si devices had a B retrograde well implanted while strained Si/SiGe devices had in-situ doped B ~7x10 17 cm -3 . 3. Electrical Characteristics Transconductance (g m ) curves as a function of VS alloy composition are shown in Fig. 2a for 0.3 μm MOSFETs. The peak enhancement in maximum g m (g m max ) over Si control devices is 240% for a Si0.7 Ge0.3 VS at a drain voltage (V d ) = 0.1 V. At V d = 1.2 V the maximum enhancement in g m max compared with Si devices is 65% (Fig. 2b). For 10 μ m gate length devices the maximum enhancement in g m max over the Si controls is 120%. The smaller enhancements in g m max in shorter channel length devices is due to SiGe self-heating. This is illustrated in Fig. 3 by the decrease in drain current (I d ) at higher V d for the strained Si0.75Ge0.25 device, which is not observed for the Si control device. I d is significantly increased for the strained Si/SiGe device compared with the Si control. At V g -V t = 2 V and V d = 1 V, I d is 0.65 mA/μm for the Si0.75Ge0.25 device and 0.4 mA/ μm for the Si control, an enhancement exceeding 60%. The higher channel mobility also causes the lower knee voltage on the I-V curves on Fig. 3. The field-effect mobility (μ e ) characteristics are shown in Fig. 4. The peak mobility for the strained Si0.75Ge0.25 device is enhanced by 115% compared with the peak mobility of the Si control device. These are the first results demonstrating that strained Si MOSFET mobility degrades at higher VS Ge compositions. The strained Si/SiGe devices exhibited lower threshold voltages than unstrained control devices (Fig. 5). The channel doping in all the devices was designed to be the same and CV measurements (Fig. 6) confirmed that there were no appreciable differences in the electrical oxide thickness (~ 6.5 nm) between the devices shown. The physical oxide thickness is measured as approximately 6 nm by TEM for the Si0.85Ge0.15VS MOSFET, in good agreement with the CV data. Therefore the differences in V t observed are primarily due to the differing electron affinities of the materials, and V g -V t was used in comparisons of electrical data. Fig. 7 shows log I d vs. V g –V t characteristics. The on-state performance is not degraded until the VS Ge composition reaches 30% (Fig. 2) but the off-state performance deteriorates at 20%. Since the sub-threshold characteristic is highly sensitive to the gate oxide interface trap density, the results indicate the effect of Ge diffusion to the surface of the strained Si channel is a negligible until a Si0.7 Ge0.3 VS is used. The μ fe - E eff relation for single and dual channel Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 2003, - 722 - A-9-4 pp. 722-723