LETTER An efficient circuit for error reduction in logarithmic multiplication for filtering applications Arjun Kumar Joginipelly 1 | Dimitrios Charalampidis 2 1 Vice President of Engineering, Freedom Electronics LLC, Kennesaw, Georgia 2 Electrical Engineering, University of New Orleans, New Orleans, Louisiana Correspondence Arjun Kumar Joginipelly, Vice President of Engineering, Freedom Electronics LLC, Kennesaw, GA 30144. Email: arjunjoginipelly@gmail.com Present address Arjun Kumar Joginipelly, 248 Harmony Cir, Acworth, GA, 30101 Summary Real-time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most time- consuming steps of the filtering operation. Log-based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log-based hard- ware multipliers by appropriately altering the filter weights and without increasing the required resources. 1 | INTRODUCTION Filtering is a computationally expensive but widely used operation in image and signal processing applications includ- ing image enhancement, 1 smoothing, 2,3 and edge detection. 4 Hardware filtering implementations often have high cir- cuitry and power consumption requirements, mainly due to the use of multipliers. Log-based multipliers convert multiplications and divisions to more efficient operators, namely, additions and subtractions, at the expense of accuracy. Mitchell 5 first proposed a method for implementing log-based multipliers using a piecewise linear approximation technique. Although the log and anti-log functions in Mitchell method are hardware efficient, they produce large aver- age errors. Attempts have been made to improve Mitchell approximation by proposing several error correction circuits. These methods include Mitchell-based methods, 6-9 lookup table (LUT)-based methods, 10-14,19,20 and region-based approaches. 15-21 This work concentrates on filtering (convolution) applications, where the filter weights are known and fixed. The proposed method employs Mitchell multiplier but optimizes the filter weights so that the convolution error is reduced. Before presenting the proposed method, some background information about existing log-based multipliers is provided. 2 | REVIEW OF LOGARITHMIC MULTIPLIERS 2.1 | Mitchell logarithmic multiplier Mitchell multiplier 5 uses a piecewise linear approximation of the log 2 (N) curve, as shown in Figure 1 for an integer N. The method is exact when N is a power of 2. The binary representation of N is Abbreviations: FF, flip flop; FPGA, field programmable gate array; IM, iterative log multiplier; LUT, lookup table; OD, operand decomposition. Received: 2 July 2019 Revised: 22 October 2019 Accepted: 11 February 2020 DOI: 10.1002/cta.2775 Int J Circ Theor Appl. 2020;1–7. wileyonlinelibrary.com/journal/cta © 2020 John Wiley & Sons, Ltd. 1