Traffic Scheduling Coprocessor with Schedulability Analysis Capability Ernesto Martins, José A. Fonseca {evm,jaf}@det.ua.pt DET / IEETA – University of Aveiro P-3810-193 Aveiro, Portugal Abstract The low processing power of typical fieldbus nodes used in real-time applications usually limits the sort of message scheduling that can be done, and precludes any kind of on-line schedulability analysis. Moving these computationally intensive tasks to dedicated hardware is an effective way to remove this limitation and achieve the best temporal determinism. This paper presents a traffic scheduling and schedulability analyser coprocessor targeted for centralised scheduling fieldbus systems. The FPGA-based coprocessor generates message schedules according to one of three different scheduling policies, and allows the number of messages and their respective parameters to be changed dynamically. The schedulability analyser capability supports on-line admission control of new messages. The paper starts by discussing the basic features which such a coprocessor should include. Then the coprocessor architecture is described together with several relevant implementation details. Finally the worst case execution times of its two main functions are derived, validating the coprocessor’s feasibility. 1. Introduction Message scheduling on a fieldbus can be done statically or dynamically. Table driven and priority-based approaches such as the ones used in WorldFIP and CAN respectively, fall in the category of static scheduling, while the best-effort approach adopted for Profibus is typical of the dynamic category [1]. In what concerns real-time applications such as process control, we are interested in scheduling messages in a way that guarantees their timeliness constraints. Here, the static scheduling approach seems to be the right choice. However if the application requirements also call for a certain operational flexibility in what concerns connecting or removing equipment from the fieldbus, or changing its configuration on-line, then the static approach is no longer adequate. In this respect, that is, in terms of operational flexibility, the dynamic scheduler would be the natural choice. However, besides its inability to guarantee timely operation by itself, the dynamic scheduler also imposes a higher run-time overhead. The run-time overhead is usually a sensitive issue due to the limited processing power generally available in fieldbus nodes. Since we are considering centralised scheduling this concerns in particular the node where the scheduler executes, known as the arbiter node. One effective solution to off-load the CPU in the arbiter node is to transfer the scheduling task to dedicated hardware working as a slave coprocessor (see figure 1). Ideally such a coprocessor should be capable of accepting dynamic changes in the message set, and run a schedulability analysis in order to guarantee that all deadlines are met. Specialised coprocessors have been used for long in implementing critical functions of hard real-time operating systems. Two basic approaches have been ... CAN Bus Node 1 Node 2 Node AN Node k Node M ... CAN Controller Coprocessor Node CPU AN: Arbiter Node Figure 1 – Typical centralised scheduling fieldbus architecture having an Arbiter Node with a scheduling coprocessor.