Accepted Manuscript Improving the performance of dual-k spacer underlap Double Gate TFET Abhinav Chauhan, Gaurav Saini, Pavan Kumar Yerur PII: S0749-6036(18)31139-X DOI: 10.1016/j.spmi.2018.10.006 Reference: YSPMI 5918 To appear in: Superlattices and Microstructures Received Date: 28 May 2018 Accepted Date: 04 October 2018 Please cite this article as: Abhinav Chauhan, Gaurav Saini, Pavan Kumar Yerur, Improving the performance of dual-k spacer underlap Double Gate TFET, Superlattices and Microstructures (2018), doi: 10.1016/j.spmi.2018.10.006 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.