Tuning SAT for Formal Verification and Testing J.UCS Special Issue Miroslav N. Velev (Reservoir Labs, New York, NY, U.S.A. velev@reservoir.com) During the last four years, tremendous progress was made in the field of Boolean Satisfiability (SAT). Now SAT solvers are 3 to 4 orders of magnitude faster, and can solve formulas that are 3 to 4 orders of magnitude bigger. SAT methods are critical to Electronic Design Automation (EDA) tool flows for state-of-the-art microprocessors. SAT-based techniques are the enabling technology behind formal verification—the mathematical proof that a design is implemented correctly. Statistics from recent cutting-edge microprocessors indicate that up to 70% of the engineering effort is spent on verification, which increasingly becomes the bottleneck when developing new products. Formal verification, presently gaining wider acceptance in industry, has the potential to significantly reduce the design time, while also guaranteeing complete correctness and avoiding costly design bugs—as expensive as 500 million dollars in the Intel Pentium processor. The five papers in this special issue present recent exciting work on tuning SAT for formal verification and testing. In the first paper, entitled MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation, Fadi Aloul from the American University of Sharjah (U.A.E.), and Igor Markov and Karem Sakallah from the University of Michigan (U.S.A.) present a static variable-ordering heuristic that operates on Boolean formulas in Conjunctive Normal Form (CNF). The derived variable order can be used in any SAT procedure, such as a SAT solver or a Binary Decision Diagram (BDD) package. Experimental results indicate that the proposed heuristic often outperforms existing state-of-the-art heuristics by a factor of 2 or more. The second paper, Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking, is by Rajat Arora from Cadence Design Systems (U.S.A.) and Michael Hsiao from Virginia Tech (U.S.A.). They perform static analysis of gate-level circuits by applying indirect and extended backward implications in order to identify implications between pairs of signals. Such implications are added as 2-literal clauses to the CNF formula derived from the gate- level circuit. Experimental results show that the added implications help to prune the search space and result in up to an order of magnitude speedup when checking the equivalence of combinational circuits. The third paper, A Signal Correlation Guided Circuit-SAT Solver, is by Feng Lu, Li-C. Wang, and Kwang-Ting (Tim) Cheng from the University of California at Santa Barbara (U.S.A.), and John Moondanos and Ziyad Hanna from Intel Corporation (U.S.A.). The authors use random simulation to identify possible correlations between pairs of signals. Then they apply two heuristics to derive conflict clauses by having a Journal of Universal Computer Science, vol. 10, no. 12 (2004), 1559-1561 submitted: 16/12/04, accepted: 22/12/04, appeared: 28/12/04 © J.UCS