Research Article Bus Implementation Using New Low Power PFSCL Tristate Buffers Neeta Pandey, 1 Bharat Choudhary, 1 Kirti Gupta, 2 and Ankit Mittal 3 1 Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India 2 Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, Delhi 110063, India 3 Department of EEE/E&I, Birla Institute of Technology, Pilani University, K. K. Birla Goa Campus, Goa 403726, India Correspondence should be addressed to Kirti Gupta; kirtigupta22@gmail.com Received 30 November 2015; Accepted 24 January 2016 Academic Editor: Stephan Giſt Copyright © 2016 Neeta Pandey et al. is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. is paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. e proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. e proposed tristate buffers consume half the power compared to the available switch based counterpart. e issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. e performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%. 1. Introduction Conventional CMOS circuits are widely used in digital integrated circuit design due to their design ease, high packing density, and negligible static power consumption [1]. e large switching noise generation in CMOS circuits restricts their use in applications pertaining to mixed-signal environment [2, 3]. Research efforts are, therefore, made towards exploring alternate low-noise logic styles. ese logic styles are based on the current steering principle [4–7] and draw a constant current from power supply and generate low switching noise in comparison to CMOS logic style. Positive feedback source coupled logic (PFSCL) style [6–10] is one among these styles that works on current steering principle and is used in high speed designs. is paper addresses implementation of PFSCL busses employed to transfer data between various peripherals inside the microprocessors based systems in mixed-signal envi- ronments. A typical bus system has many tristate buffers attached to a common node. e study of PFSCL tristate buffers/inverters reveals that only two topologies are available [11]. ese topologies use either a switch or a sleep transistor to attain the tristate behavior. e suitability of the sleep transistor and the switch transistor based PFSCL tristate buffers [11] in bus system implementation is investigated and the drawbacks are identified. New PFSCL tristate buffers for this purpose are presented in this work. e paper is organized in six sections including the intro- ductory one. A brief review of available PFSCL tristate buffers is presented in Section 2. Design issues in implementing bus system using the available tristate buffers are identified in Section 3. ereaſter, the new PFSCL tristate buffer topologies are presented in Section 4. eir performance comparison and suitability in bus implementation are demonstrated through SPICE simulations by using TSMC 180 nm CMOS technology parameters in Section 5. e impact of parameter variations and the effect of parameter mismatch are also studied for the proposed topologies. Lastly, the paper is concluded in Section 6. Hindawi Publishing Corporation Active and Passive Electronic Components Volume 2016, Article ID 4517292, 8 pages http://dx.doi.org/10.1155/2016/4517292