ISSN (Online) 2321 – 2004 ISSN (Print) 2321 – 5526 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING Vol. 2, Issue 2, February 2014 Copyright to IJIREEICE www.ijireeice.com 948 Design Approach towards High Performance Memory of 6 Transistors SRAM Cell Using 45nm CMOS Technology Nupur G.Nanoti 1 , Prafulla D.Gawande 2 PG student, Department of Electronics & Telecommunication, Sipna’s college of Engineering & Technology, Amravati, Maharashtra, India 1 Associate Professor, Department of Electronics & Telecommunication, Sipna’s college of Engineering & Technology, Amravati, Maharashtra, India 2 Abstract: Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The amount of memory required in a particular system depends on the type of application, but, in general, the number of transistors utilized for the information (data) storage function is much larger than the number of transistors used in logic operations and for other purposes. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development towards more compact design rules and, consequently, toward higher data storage densities. The trend towards higher memory density and larger storage capacity will continue to push the leading edge of digital system design. The Microwind 3.1 software will allow designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211mwatt), high speed static RAM area efficient chip is designed using 45 nm CMOS technology. Keywords: 6T Static RAM cell, memory, 45nm VLSI technology, low power. I. INTRODUCTION Static Random Access Memory: This form of semiconductor memory gains its name from the fact that, unlike DRAM, the data does not need to be refreshed dynamically. It is able to support faster read and write times than DRAM (typically 10 ns against 60 ns for DRAM), and in addition its cycle time is much shorter because it does not need to pause between accesses. However it consumes more power, is less dense and more expensive than DRAM. Effort has been taken to design Low Power, High performance Static RAM, using VLSI technology. The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirement. When the requirements are not met, the design has to be improved. More simplified view of the VLSI technology consists of various representations, abstractions of design, logic circuits, CMOS circuits and physical layout. [11] This paper introduces design aspects for layout design of static RAM memory using VLSI technology. This Static RAM is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. There is a large variety of types of ROM and RAM that are available. These arise from the variety of applications and also the number of technologies available. This means that there are a large number of abbreviations or acronyms and categories for memories ranging from Flash to MRAM, PROM to EEPROM, and many more. [14] II. LITERATURE REVIEW From the rigorous review of related work and published literature, it is observed that many researchers have designed MOS memory by applying different techniques. Researchers have undertaken different systems, processes or phenomena with regard to design and analyse MOS memory. Since in the real world today VLSI/CMOS is in very much in demand, from the careful study of reported work it is observed that very few researchers have taken a work for designing MOS memory with CMOS/VLSI technology. In July 2008, B. Amelifard, F. Fallah and M.Pedram was worked on a method which based on dual-Vt and dual-Tox assignment to reduce the total leakage power dissipation of static random access memories(SRAM).[9] In September-Octomber 2010 Dr. Ujwala A.Belorkar has researched on application of 45nm VLSI technology to design layout of static RAM memory. [13] From the careful study of reported work, it is observed that researchers have proposed various techniques to design the chip and to improve its characteristics and various parameters but up to the result of my survey regarding 6T static RAM cell design. It is also well known to that; VLSI technology is the fastest growing field today. And according to Moore’s law which state that the numbers of transistors on an integrated circuit will double every 18 months. By scaling down the technology, we can optimize the parameters like power consumption.