micromachines Editorial Special Issue on Networks-on-Chip Again on the Rise: From Emerging Applications to Emerging Technologies Davide Bertozzi 1, *, José L. Abellán 2 and Mahdi Nikdast 3   Citation: Bertozzi, D.; Abellán, J.L.; Nikdast, M. Special Issue on Networks-on-Chip Again on the Rise: From Emerging Applications to Emerging Technologies. Micromachines 2021, 12, 1570. https:// doi.org/10.3390/mi12121570 Received: 4 December 2021 Accepted: 10 December 2021 Published: 17 December 2021 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affil- iations. Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). 1 Engineering Department, University of Ferrara, 44122 Ferrara, Italy 2 Computer Science and Engineering Department, Universidad Católica de Murcia (UCAM), 30107 Murcia, Spain; jlabellan@ucam.edu 3 Electrical and Computer Engineering Department, Colorado State University, Fort Collins, CO 80523, USA; mahdi.nikdast@colostate.edu * Correspondence: davide.bertozzi@unife.it Twenty years after the advent of interconnection networks to tackle the on-chip communication bottleneck [1], integrated computing platforms are again interconnect- dominated. First, the future of computing beyond Moore’s law and Dennard scaling is moving towards Systems-in-Package (SiP) based computing platforms that leverage ad- vanced integration technologies such as 2.5D or 3D stacking [2]. In this context, emerging interconnect technologies aim at sustaining the levels of system integration by deliver- ing performance and power metrics that are out-of-reach for conventional electronics [3]. Second, the advent and consolidation of data-intensive applications from artificial in- telligence and big data analytics is putting unprecedented pressure on interconnection fabrics at each layer of the compute hierarchy [4]. Third, the emergence of novel comput- ing paradigms consisting of domain-specific accelerators, optical computing, quantum computing or neuromorphic computing can truly make an impact provided matching interconnect architectures and technologies are developed [5]. Fourth, the increased usage of networks-on-chip (NoCs) and their distributed nature across integrated circuits have made them a focal point of potential security attacks [6]. In this context, network-on-chip research is again on the rise, thereby generating a second wave of “communication-centric designs.” Unlike the early days, when the first NoC architectures were designed, the same concept nowadays holds at a radically different abstraction level: it refers to novel system-level design paradigms leveraging the enabling features of communication architectures and emerging technologies. Thus, NoC research is even more exciting than it used to be because researchers have to break barriers between disciplines and take a fundamental cross-layer approach to design and optimization of more complex NoCs. This Special Issue provides an overview of the ongoing research efforts that are trying to bring on-chip interconnection networks into new ground. It consists of eight papers covering some of the most sensitive aspects of the ongoing network-on-chip evolution, as hereafter illustrated. (1) Most of the papers deal with the increasing complexity of efficient network- on-chip management in the presence of multi-programmed platforms (where several applications are consolidated onto a unified parallel hardware platform) and/or data- intensive applications, raising unprecedented mapping, congestion control and bandwidth allocation concerns. F. Ge et al. [7] target the simultaneous deployment of multiple applications onto the same NoC-based system. Among other application domains, this scenario is of interest for the Edge computing environment, where multiple Internet-of-Thing services contend for shared resources on cost-constrained computational platforms. A genetic algorithm is used for application mapping into potential regions, while a simulated annealing algorithm generates the optimal placement for the multi-application mapping regions. Micromachines 2021, 12, 1570. https://doi.org/10.3390/mi12121570 https://www.mdpi.com/journal/micromachines