A precision comparator design with a new foreground offset calibration technique Islam T. Abougindia 1 • Ismail Cevik 1 • Fadi N. Zghoul 2 • Suat U. Ay 1 Received: 15 December 2014 / Revised: 18 March 2015 / Accepted: 23 March 2015 / Published online: 1 April 2015 Ó Springer Science+Business Media New York 2015 Abstract This paper presents a new digitally-assisted analog foreground comparator offset calibration technique that is fast, compact, low-power, precise, and linear. Non- linear input referred DC offset voltage of a comparator used in an analog-to-digital converter (ADC) is considered as the most important factor that degrades performance, especially for ADC architectures that utilize multiple comparators, such as flash ADCs. This paper discusses the causes of various types of offsets as well as techniques for cancelling them in dynamic latched comparators. Both background and foreground offset calibration techniques used in dynamic comparators are explained. Three popular circuit implementation approaches for foreground calibra- tion are reviewed. A novel coarse–fine calibration (CFC) technique is introduced presenting concept of operation and its effectiveness over other available analog fore- ground offset calibration techniques. Simulation and mea- surement results of dynamic comparators that were fabricated in 2P3M, 3.3 V, 0.35 lm CMOS process are presented. It was shown that the proposed CFC technique achieves better performance than other digitally-assisted analog calibration techniques without requiring high- resolution ([8-bit) trimming digital-to-analog converters while providing compact, high-speed, low-power, and lin- ear offset correction over the full offset range of up to ±100 mV. Keywords Comparator offset  Offset correction  Analog–digital converter  Comparator precision  Offset trimming  Coarse–fine calibration  Offset correction techniques 1 Introduction Comparators are considered to be the most important blocks in analog-to-digital converters (ADCs). They are widely used as the decision-making circuit during con- version of an analog signal into digital. Comparators could be designed to work continuously (static) or to make de- cision after being initiated with a clock signal (dynamic). Dynamic comparators have replaced static comparators in many applications to minimize power consumption without trading off speed. These comparators use positive feedback to achieve high-gain, high-speed, low-power, and rail-to- rail output swing. Consequently, minimum size transistors are often used to reduce parasitic capacitances that limit speed and bandwidth and increase power consumption. On the other hand, minimum size transistors exhibit large physical and electrical mismatches even if they are laid out with excellent symmetry and placed with minimum prox- imity to each other on silicon [1]. Mismatches are categorized as static (i.e., threshold voltage and transcon- ductance) and dynamic (i.e., slew rate mismatch between different nodes) mismatches [2, 3]. These mismatches cause random offset voltages in comparators degrading their performance. Several mixed-mode foreground and background offset calibration techniques have been proposed for designing precision comparators in the past [4–10]. Most analog calibration techniques require integrated trimming digital- to-analog converters (DACs). Digital calibration words are & Suat U. Ay suatay@uidaho.edu 1 Electrical and Computer Engineering, University of Idaho, Moscow, ID 83844, USA 2 Electrical Engineering, Jordan University of Science and Technology, Irbid, Jordan 123 Analog Integr Circ Sig Process (2015) 83:243–255 DOI 10.1007/s10470-015-0520-4