SETIT 2009 5th International Conference: Sciences of Electronic, Technologies of Information and Telecommunications March 22-26, 2009 – TUNISIA - 1 - Design and Implementation of a Real Time FPGA Based CFAR Processor for Radar Target Detection Using ML403 FPGA Development Board Boualem MAGAZ *, ** , Toufik MABED ** and Ali ABBADI ** * Ecole Nationale Supérieure Polytechnique, Algiers, Algeria boualem.magaz@enp.edu.dz ** Research and Development Center, Algiers, Algeria md_toufik16@yahoo.fr khaledkhald@yahoo.fr Abstract: The improvement in the development of theoretical aspect of CFAR radar detection is advanced and very promising, yet the practical hardware aspect is still beyond the required high computational signal processing operations. In this paper, a configurable Field Programmable Gate Array (FPGA) based hardware architecture for Ordered Statistics (OS)-CFAR processor for radar target detection is presented. The proposed architecture is based on an efficient procedure for FPGA implementation of the OS-CFAR detector, based on the (N-K+1)-th maximum determination. By showing that the determination of the K-th order out of N reference cells is equivalent to selecting the (N + 1 - K)-th maximum, the detector that uses N reference cells can be implemented using only (N-1) comparators and (N-1) inverters. The proposed structure, adapted to the ASR-9 radar parameters, is designed, implemented, and evaluated on the ML403 FPGA board. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The system has the advantages of being simple, fast, and flexible with low development cost. For a reference window of 16 range cells, the experimental results carried out using Xilinx development kit showed that the proposed architecture works properly with a processing speed of 50MHz (up to 122 MHz using external clock). The execution time to perform the overall OS-CFAR detection algorithm is 0.819ms for a data set of 1000 range cells. The FPGA implementation results are presented and discussed. Key words: FPGA, Implementation, OS-CFAR processor, Radar. INTRODUCTION Detection of target in a background of clutter is a problem of interest in radar field. In order to improve such detection system, the designer usually prefers a constant false alarm rate. To achieve this purpose, the actual interference power must be estimated from the data in real time, so that the threshold can be adjusted to maintain the desired probability of false alarm (Pfa). A detection processor that can maintain a constant Pfa is called Constant False Alarm Rate (CFAR). Finn and Johnson [FIN 68] developed a theory based on arithmetic mean of the neighboring resolution cells of the cell under test. This is known as Cell Averaging CFAR detector. The CA-CFAR detector was shown to be efficient in homogenous environment. In fact, the probability of detection approaches the classical Neayman-Pearson case where the mean level of clutter is known a priori, provided that these cells do not contain non- homogenous samples. However, the detector based on order statistics (OS-CFAR) proposed by Rohling [ROH 83] provides inherent protection against serious performance degradation in the presence of non- homogenous samples. The OS-CFAR processor estimates the noise power simply by selecting the Kth largest cell in the reference window; the threshold is obtained from one of the ordered samples of the reference window. The range samples are first ordered according to their magnitudes, and the statistic Z is taken to be the Kth largest sample. Although the improvement in the development of the theoretical aspect of CFAR detection is advanced and very promising, yet the practical hardware aspect is still beyond the required high computational signal processing operations. Nowadays, Field Programmable Gate Arrays (FPGAs) have emerged as an attractive