ISSN (Online) 2321 – 2004 ISSN (Print) 2321 – 5526 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING Vol. 2, Issue 3, March 2014 Copyright to IJIREEICE www.ijireeice.com 1262 Low-Power Architectures and Self-Calibration Techniques of DAC for SAR-ADC implementation Atul Thakur 1 and Alpana Agarwal 2 ECED Department, Thapar University, Patiala, India 1 Associate Professor, ECED Department, Thapar University, Patiala, India 2 Abstract: SAR-ADC is best suited for low power applications where power has a trade-off with speed. Use of redundant circuitry reduces the on chip area making it cost effective. DAC is one of the components of SAR-ADC that introduces error voltage due to mismatch and consumes large power other than comparator. Low power DAC architectures have been studied and analysed. To account for capacitor mismatch issues self-calibration techniques have been discussed and analysed for 14-bit DAC implementation. All the architectures have been analysed for 100KS/s with 1.6MHz clock speed in 180nm technology with supply voltage of 1.8V. EDA tool used for design analysis is Cadence® Spectre®. Keywords: Successive Approximation Register Analog-to-Digital Converter (SAR-ADC), Digital-to-Analog Converter (DAC), Electronic Design Automation (EDA), Least Significant Bit (LSB), Calibration. I. INTRODUCTION For the most biomedical applications stringent low power design with comparable resolution is preferred. Among the various ADC architectures SAR-ADC fits the most as because of its redundant circuitry use at relative low clock rates reduces power dissipation effectively [1]. All though resolution is not as good as of Sigma-Delta ADC architecture but its oversampling rate introduces countable power dissipation. DAC in SAR-ADC architecture consumes noticeable power and is counted for introducing errors due to mismatch and thermal noise. Instead of resistive DAC the capacitive DAC architectures are preferred as it reduces extra need of sampling circuitry; consume less power and saves on chip area. Beside this other issues comes into picture like capacitor mismatch, thermal noise limitations, parasitic influence, etc. But the pros overcome the cons of using capacitive architecture. There are many calibration techniques that reduce error voltage due to capacitive mismatches like foreground and background calibration techniques. Here in this paper foreground calibration techniques specifically Self- calibration technique is analysed and discussed. II. DAC ARCHITECTURES For SAR-ADC implementation capacitive DAC architectures are commonly used for low power designs these day‟s because of their enormous advantages over other DAC architectures. A. Charge Scaling DAC Charge scaling DAC is preferred over the other architectures because of ease of design and the three operations being performed on the same structure i.e. (1) Sampling (2) Subtraction node, and (3) DAC operation. Charge scaling DAC works on the principle of charge storage and charge redistribution. During the sampling phase the charge is stored in the capacitors corresponding to the voltage difference (VIN-Vbias) across its plate‟s i.e.  = ∗   =  −  During the conversion time the charge is distributed across all the capacitors. All the capacitors used are binary weighted with respect to unit capacitance C (in fF) as shown in Fig. 1. Fig. 1 Capacitive Charge scaling DAC Impact of thermal noise and quantization noise is taken into consideration for calculation on unit capacitance limit and their sum should be limited to the half of DAC-LSB.     +  2 12 ≤  2 ..(1) Where,  = 1.8 2 14 = 0.109 ∴  ≥ 2.0589  for T = 300 0 K ..(2) Also,   for the given architecture can be calculated as:   = 16384 ,   =   ..(3) From eqns. (2) and (3) ≥ 0.12567 The imposed limitation for the minimum capacitance in 180nm technology is 1.2 fF. At this minimum value a little capacitance mismatch can introduce large (more than 1LSB) error voltage at output node. Thus for the analysis 15fF of unit capacitor is used. For higher resolution DAC‟s (i.e. ≥ 10-bit) total capacitance of DAC increases exponentially thus an