Vol.:(0123456789) The Journal of Supercomputing https://doi.org/10.1007/s11227-023-05151-0 1 3 FPGA implementation of hardware accelerated RTOS based on real‑time event handling Ionel Zagan 1,2  · Vasile Gheorghiță Găitan 1,2 Accepted: 28 February 2023 © The Author(s) 2023 Abstract Actual trends in the real-time system feld consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the imple- mentation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on syn- thesizing in feld-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efcient hardware scheduler micro-architecture, from which a remarkable ef- ciency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in dif- ferent confgurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper. Keywords nMPRA architecture · Hardware RTOS · Fast context switch · Resource multiplication 1 Introduction Due to the complexity of the real-time applications and very short response times in the industrial, medical and automotive felds, the design and development of hardware systems with increased computing power was necessary; more convenient * Ionel Zagan zagan@usm.ro * Vasile Gheorghiță Găitan vgaitan@usm.ro 1 Stefan cel Mare University of Suceava, 720229 Suceava, Romania 2 Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD), Stefan cel Mare University, Suceava, Romania