International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value (2015): 78.96 | Impact Factor (2015): 6.391 Volume 6 Issue 3, March 2017 www.ijsr.net Licensed Under Creative Commons Attribution CC BY Design of Second Order Discrete Time Sigma Delta Modulator for High Resolution Applications R Anil Kumar 1 , E Srinivas 2 1 M. Tech Student in VLSI System Design, Anurag Group of Institutions, Hyderabad, India 2 Assistant Professor, VLSI System Design, Anurag Group of Institutions, Hyderabad, India Abstract: Aim of This work is to Design a second order discrete time sigma delta modulator for low frequency high resolution applications, which can be used in data converters (sigma delta ADC) where high resolution is required for more accuracy in signal processing’s. A real world is analogue but easier to process digital data ex: speech, image processing’s. Analog signal contains too much unnecessary data ADC samples the data and splits into finite information. Sigma delta ADC is very much suitable for less area low frequency and high resolution data conversions. Now the aim is to design a sigma delta modulator in which these parameters plays major role 1) resolution 2) order 3) OSR 3) power consumption 4)SNR 5)SNDR 6)dynamic Range. This design is carried out with the 180nM CMOS technology at an operating voltage of ±700mV, and the results are tested with the help of Cadence Virtuoso Spectre Circuit Simulator. Keywords: op-amp, 180nM, sigma-delta modulator, SDM 1. Introduction All available natural signals are analog signals but it is easy to process digital signals, so there is always demand for analog to digital and digital to analog convertors. There are many ADC architectures are available but sigma delta ADC will have its unique advantage comparing with others .in general there are two types of ADC architectures are available they are one is nyquist rate ADCs and the second one is oversampling ADCs, these sigma delta ADCs will comes under the oversampling ADCs. The oversampling technique will avoids the use of sharp filters or aliasing filters, by using high gain and full swing amplifiers the signal degradation in intermediate stages can be avoided. The Sigma Delta ADC consists of manly two blocks they are modulator and decimation filter. High resolution is the main key factor which gives the unique position to the sigma delta modulator ADC among other ADCs. Sigma delta ADC consists of two blocks they are one is modulator and the other one is decimator. The current work concentrates on the design of Discrete Time second order sigma delta modulator. To achieve the target performances of sigma delta modulator, a new approach was made as design of low voltage & low power modulators for that purpose, the design of low voltage and low power high performance operational amplifier is required. Low voltage means less than half of the nominal voltage, for 180nM nominal voltage is 1.8V but the current work designs the whole module with operating voltage of ±700mv.and the low power means the power consumption should be in the range of 1µ to some tens of µwatts. This prototype modulator achieve excellent performance constraints for a given bandwidth and resolution in spite of low supply voltages. In the design of low order modulators aiming at achieving high resolution with limited power budget particular attention should be given to power- resolution trade-offs involving the design of multi-bit quantizers. A smaller quantizer input range translates in a lower linearity requirement for the last integrator and at the same time in a smaller input offset for the quantizer comparators. These requirements are conflicting in terms of power demand especially in low voltage nanometer technologies [2]. This paper is organized in the following manner. Section II describes the operation and block diagram of sigma-delta modulator. Section III discusses the design of operational - amplifier and its power optimization. Section IV details the simulation results of proposed sigma delta modulator and comparison. Section V provides conclusion and future scope. 2. Block Diagram The block diagram of discrete time sigma delta modulator consists of mainly 1) Sampling circuit: it consists of a switch when it is on signal will be transferred otherwise maintains the same level; it is used to sample the input signal. 2) 2 nd order discrete time sigma delta modulator: It consists of two integrators with mixer circuit as shown in block diagram. 3) Comparator: It is used to compare the signal from output of integrator with the reference signal 4) DAC: Here 1-bit DAC is used; output pulse signal is given as the feedback to the input through DAC, and for better noise shaping feedback is given to the second integrator also through mixer. The organization of above blocks can be shown as Paper ID: ART20171418 326