On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements Vikram B. Suresh, Priyamvada Vijayakumar and Sandip Kundu University of Massachusetts, Amherst, USA {vsuresh, vijayakumar, kundu}@ecs.umass.edu Abstract— Current printability issues can be attributed to sub- wavelength lithography and its sensitivity to manufacturing process variations. Resulting process variations cause performance, yield and reliability problems. As noted in ITRS, conventional burn-in test is losing cost-effectiveness in reliability screening. In this paper, we use lithography process corner information in reliability screening. The lithographic process corner information is decoded from circuit measurements using a tester. We propose two methodologies for binning of dies based on Mean Time to Failure (MTTF). Lithography aware LUT based binning uses pre-estimated MTTF values to bin dies based on the detected litho-process corner. Lithography aware pattern based binning uses test patterns specific to litho-process corner along with existing techniques like burn-in test or Electrical Linewidth Metrology (ELM). Accurate determination of die level process corner is an important step employed in the proposed methodology. This work aims at: a) test Pattern generation for increased reliability test coverage incorporating manufacturing variations, b) utilization of die based process corner information for choosing the best test pattern set for improved fault coverage, c) achieving acceleration of infant mortality within the manufacturing test flow, and d) die-level determination of MTTF incorporating lithography process variation and hence decreasing the binning-yield loss. Experiments on ISCAS’85 circuits for varying exposure dose and de-focus values show an average variation of 20-30nm in interconnect widths, resulting in a deviation of as much as 40% in the estimated MTTF. It is also observed that, for maximum fault coverage, the test vector set changes in size and pattern across various process corners. Keywords-Lithography variation; Electromigration; Reliability; MeanTime To Failure (MTTF) I. INTRODUCTION Process variation is being regarded as roadblock to future technology scaling [1]. Process variation can be random or systematic. It is generally categorized as Intra-die, Inter-die, wafer-to-wafer and lot-to-lot variability [2]. It should be noted that all systematic variations have deterministic source. But some of these systematic variations are unknown at the time of design or is too complex to model and thereby are treated as random. Such variations are expected to have a varying degree of spatial correlation. With smaller interconnect widths and spacing, the conventional assumption of perfect spatial correlation between areas within the die does not exist and hence impacts design yield and reliability. For sub-90nm nodes the die-to-die 3σ/μ variation is greater than 15% over half a wafer [1]. Thus, as we move into smaller technology nodes, both intra-die and inter-die random variations have a greater impact than wafer-to-wafer or lot-to-lot variations. Hence, an accurate and justifiable model of spatial variability is critical in reliability prediction and leveraging the variation data in the binning process. Sub-wavelength printability issues are sensitive to manufacturing variations like overlay errors, defocus and exposure dose variations. The variation in lithography process manifests in the form of critical dimension variations such as Line Edge Roughness (LER), Line Width Roughness (LWR) and corner rounding due to Across the Chip Linewidth Variations (ACLV) [3]. Hence, Resolution Enhancement Techniques (RET) like Optical Proximity Correction (OPC), Off-Axis Illumination (OAI) and Phase Shift Masking (PSM) are being applied in current image transfer systems. These techniques can only help mitigate lithography introduced variation but cannot completely eliminate them. Many sources of systematic variability can be associated to the characteristics of the manufacturing process adopted. Manufacturing processes employed in nanoscale CMOS technologies use sub- wavelength lithography. This has resulted in greater lithography induced variations, which affect the parametric yield, functional yield, reliability and hence the overall profitability of a product [1]. Thus, there is a need for incorporating lithography analysis in obtaining the spatial variability data for better reliability prediction. Transistors and interconnects that are affected by variability [4] are analyzed further for reliability prediction. Several testing methodologies are used to check the quality and reliability of the chips. Pre burn-in, burn-in and Final Test are conducted at various testing stages of the die [6] to check the quality of the circuit. An ideal burn-in test should screen the defective dies without damaging the good chips [6].A proper burn-in process should induce early failures of weak devices and screen out those with extreme parametric shift. As noted in ITRS, conventional burn-in test is losing cost-effectiveness in reliability screening. Product lifetime determination is becoming tough with conventional reliability assessment methodologies. In the sub-micron era, lifetime of transistor or wire is extrapolated from accelerated testing and the product is deemed reliable. Greater need to obtain accurate reliability information has led to research focusing on analyzing MTTF of a transistor or a wire at different levels of abstraction. MTTF of a wire is a metric that defines when a wire would physically break down and stop functioning [12]. This MTTF data is further utilized for reliability analysis in the conventional methodology. The novel methodology proposed in this paper aims at a) test Pattern generation for increased reliability test coverage 2011 IEEE Computer Society Annual Symposium on VLSI 978-0-7695-4447-2/11 $26.00 © 2011 IEEE DOI 10.1109/ISVLSI.2011.66 248