1050 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 27, NO. 12, DECEMBER 2017 An Efficient Estimation of Power Supply-Induced Jitter by Numerical Method Jai Narayan Tripathi , Member, IEEE, and Flavio G. Canavero Fellow, IEEE Abstract—This letter presents an efficient and generic method- ology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach. The methodol- ogy is described in detail through an example of a voltage-mode driver circuit. There is a significant speed-up reported compared with the simulations by a commercial simulator. Index Terms— Numerical methods, power supply-induced jitter (PSIJ), power supply noise, voltage-mode driver circuit. I. I NTRODUCTION T HE low-power requirements of semiconductor devices and the increasing demand of faster switching make it difficult for the packaging industry to cope with the VLSI industry [1]. The passive interconnects have bandwidth limi- tation that limits the speed and functionality of the high-speed systems. Due to this, the system specifications are becoming more and more stringent. In modern high-speed systems, maintaining jitter is one of the major issues as it is considered to characterize the signal/power integrity of the system. Power supply-induced jitter (PSIJ) is one of the major subcomponents of jitter, which is caused by the noise in power delivery networks (PDNs) [2]. There are several techniques available in literature to estimate the PSIJ, using analytical methods [3]–[8]. This letter attempts to estimate the PSIJ efficiently by a numerical method. The proposed methodology is novel and advantageous as it does not require netlist-based simulations, and since it is based on a root-finding approach, analytical approximations are not required. The methodology is validated by an example of the voltage- mode driver circuit but can be extended to any circuit in a similar way. For the context of this letter, the details of basic circuit analysis are skipped. II. CIRCUIT DESCRIPTION AND EQUIVALENT MODEL Fig. 1 shows the circuit of a voltage-mode driver commonly used in high-speed transmission links for differential-mode operation [7]. There is an H-bridge with two complementary bitstreams for enabling the differential output. The source of transistor M 0 is kept at a regulated voltage by a closed-loop using an op-amp. M 1 and M 4 switch together and provide a low-impedance path for current from M 0 to the load, when Manuscript received August 17, 2017; accepted September 18, 2017. Date of publication October 26, 2017; date of current version December 4, 2017. (Corresponding author: Jai Narayan Tripathi.) J. N. Tripathi is with STMicroelectronics Pvt. Ltd., Greater Noida 201308, India (e-mail: jainarayan.tripathi@st.com). F. G. Canavero is with the Politecnico Di Torino, 10129 Torino, Italy (e-mail: flavio.canavero@polito.it). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2017.2760740 Fig. 1. Circuit of a voltage-mode driver [8]. Fig. 2. Equivalent circuit for modeling rising edges [7]. M 2 and M 3 provide high impedance path, and vice versa in the next cycle as the input patterns are complementary. V DD is the power supply for the circuit, V DD1 is the same for the op- amp, and v n (t ) is the noise in the power supply of the circuit. C 1 , C 2 , and C cm with two 50  resistors combinedly act as the differential load and the differential voltage is measured across terminals X and Y . In order to analyze the circuit for the estimation of PSIJ, the circuit is first analyzed for large-signal voltages. There are complementary data patterns for two different paths of the bias current; one path at a time (whichever is having low impedance) can be considered for analysis. Since the node where the voltage is regulated by op-amp is stable, it can be assumed as a voltage source for the circuit. Fig. 2 shows a circuit, which represents a case when M 2 is in saturation and M 3 is in linear region. V OH is the output high voltage. Using this equivalent model, by nodal analysis, the differential voltage across the load can be given as v L (t ) = v X (t ) − v Y (t ) = A + 3  i =1 B i e d i t (1) 1531-1309 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.