An Error Detection and Correction System based on Associative Memories Constantin ANTON, Lauren iu IONESCU, *Ion TUT NESCU, Alin MAZ RE, Gheorghe ERBAN, Adriana OPREA Faculty of Electronics, Communications and Computers - University of Pite ti, Romania {constantin.anton, laurentiu.ionescu, ion.tutanescu, alin.mazare, gheorghe.serban, adriana.oprea}@upit.ro * Corresponding author Abstract - Associative memories have the property to allow the searching of a binary stored value, having as an input data a partial amount of this value. This property can be used in communication for detecting and correcting the errors encountered in the communication channel. We present in our paper a solution to design and implement a hardware errors’ correction and detection circuit using associative memories. In the final part of our paper, an analysis was realized in order to compare the obtained experimental results with performances of other implemented hardware systems. Keywords - errors’ correcting codes, encoder, decoder, word code, associative memories, Field Programmable Gates Array (FPGA). I. INTRODUCTION The usage of error correcting control is very important in the modern communication systems. This paper presents the prototyping of a BCH encoder and decoder using associative memories. BCH codes (Bose, Chaudhuri, and Hocquenghem) are being widely used in communication networks, computer networks, satellite communications, magnetic and optic storage systems. BCH codes can be defined by two parameters which are: the length of code words, n, and the number of errors to be corrected, t. These codes operate over finite fields or Galois fields. BCH codes are a class of cyclic codes whose generator polynomial is a product of distinct minimal polynomials corresponding to , 2 , … , 2t , (1) where ( ) m GF 2 ∈ α is a root of the primitive polynomial g(x) [1] [8]. An irreducible polynomial g(x) of degree m is said to be a primitive if only if it divides polynomial form of degree n, 1 + n x for no n < 1 2 − m . (2) In fact, according to [2], every binary primitive polynomial g(x) of degree m is a factor of 1 1 2 + − m x . For our application we use the generator polynomial: 1 ) ( 2 4 5 8 10 + + + + + + = x x x x x x x g , (3) which can detect 6 errors and correct 3 erroneous bits. II. HARDWARE CIRCUITS FOR ERRORS DETECTION AND CORRECTION Field-Programmable Gate Arrays (FPGA) have become one of the key digital circuit implementation media over the last decade [3]. One bit patterns produce operational circuits which can be used in many areas, like the communication systems. FPGA represent a compromise between circuits with microprocessor and ASIC (Application Specific Integrated Circuits) [4] [7]. First, they present flexibility in programming, called here reconfiguration, which is a feature for microprocessors. Even if FPGA cannot be programmable while operation, they can be configured anytime is needed, having a structure based on RAM programmable machines, as we can see in Figure 1. On the other hand, they allow parallel structures’ implementation, with a response time which is smaller than those of a system with microprocessor. Our hardware scheme for errors’ detection and correction is based on a polynomial generator. The proposed system is based on the use of reconfigurable FPGA circuits for a hardware implementation of error detection and correction algorithm. Figure 1 - Communication system with hardware errors’ detection and correction. III. ENCODER AND DECODER: DESIGN AND IMPLEMENTATION We have designed the encoder and decoder using dedicated Boolean circuits. Thus, the encoder will be attached as a physical device to any system which transmits data through a communication channel, while the decoder will be attached to the system which receives the data. 20th Telecommunications forum TELFOR 2012 Serbia, Belgrade, November 20-22, 2012. 978-1-4673-2984-2/12/$31.00 ©2012 IEEE 568