Coding for Correcting Insertions and Deletions in Bit-Patterned Media Recording Anantha Raman Krishnan, and Bane Vasic, Senior Member, IEEE Abstract—Bit-patterned media is a novel technology for mag- netic data storage that is poised to increase recording density beyond 1 Tb/sq. in. However, a significant concern in BPMR is the stringent requirements for synchronization between write clock and island position, errors in which may manifest as insertions and deletions. In this paper, we introduce a method for compen- sating for synchronization errors by using conventional error- correcting codes. We present a numerical study that provides bounds on achievable coding rates. We also perform a simulation study to demonstrate the applicability of the proposed scheme in practical systems. I. I NTRODUCTION In the past few years, many novel technologies have been proposed to increase storage densities of magnetic recording systems over 1 Tb/in 2 , bit-patterned media recording (BPMR) [1] being the most promising of them. However, BPMR presents challenges that were not a concern in conventional magnetic recording systems, e.g., write synchronization [2]. In BPMR, a high degree of synchronization is required between the write clock and island positions. Errors in synchronization may manifest as insertions or deletions in the bit-stream read out [3]. It is vital that robustness to synchronization errors be maintained. Such robustness can be achieved by using codes capable of correcting insertion and deletion errors, subsequently compensating for written-in errors during the readback. This motivates the investigation of the nature of information transmission in channels with synchronization errors. For a number of years, characterization of channels with synchronization errors has been an active field of research (e.g. [4] and [5]). In the recent past, this has been further driven by aforementioned systemic requirements in BPMR. However, such channels are are not characterized fully, with only bounds available on capacity of channels (see [6] and references therein for a detailed discussion). Another related area of research has been the design of systems that compensate for in- sertion and deletion errors. Levenshtein [4] provided a number- theoretic construction of codes capable of correcting a single error (synchronization error or error in bit-value). Although a simple decoding algorithm for this class of codes exists [7], these codes are not systematic, thereby making implementa- tion non-trivial for all but the smallest-length codes. Davey and MacKay [8] proposed watermark codes with a proba- bilistic decoding algorithm operating on a two-dimensional (2D) trellis for error-correction in insertion/deletion channels. A. R. Krishnan, and B. Vasic are with the Department of Electrical and Computer Engineering, The University of Arizona, Tucson, AZ, 85721 USA e-mail: {ananthak, vasic}@ece.arizona.edu. This work is supported by INSIC- EHDR and IDEMA-ASTC Subsequently, marker codes based on a similar decoder was proposed by Ratzer [9]. These schemes, though observed to be powerful, rely on complex decoding algorithms which are not conducive to system-level implementation. More recently, Ng et al. [3] developed a scheme based on 2D error-correcting codes for insertion/deletion errors, in the context of BPMR. Again, implementation in real-life systems necessitates multi- track processing – a considerable challenge with the current state of the art in the technology. One of the difficulties in addressing the problem of code- construction is the fact that channels with synchronization er- rors have infinite memory, i.e., a synchronization error affects all subsequent symbols. In this paper, we introduce a coding scheme by which it is possible to transform certain channels with synchronization errors into memoryless channels. This naturally leads to a information encoding scheme by which conventional error-correcting codes may be used to compen- sate for synchronization errors. In addition, this method is advantageous as it lends itself to single-track processing. We also provide a brief numerical study of the capacity study of this class of channels, and show some results of use of error- correcting codes on these channels. The rest of the paper is organized as follows: Section II introduces our channel model and data encoding scheme. A numerical analysis of channel capacities obtained is pro- vided in Section III. In Section IV, we show results of our experiments conducted to prove the applicability of our methodology. Finally, Section V concludes the paper. II. CHANNEL MODEL In [3], Ng et al. illustrate how jitters in island positions in BPMR may manifest as synchronization errors, with errors occurring in arbitrary positions. In this section, we give a brief description of a modified synchronization-error channel we consider, and explain how information may be transmitted through this channel. Consider a channel with binary input and output alphabets. The most general formalism that describes synchronization and bit-flip error is a finite-state machine [8]. At time t i a bit may be inserted with a probability p i , deleted with a probability p d , or successfully transmitted with a probability 1 − p i − p d . The possibility of a change in the value of the transmitted bit can also be encompassed by this model. In this work, we consider a modification of the channel described above wherein the number of consecutive synchro- nization errors is restricted, and operates on individual runs of binary sequences. Here, we define the term run in a binary se- quences as an occurrence of k consecutive, identical symbols. U.S. Government work not protected by U.S. copyright This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE Globecom 2011 proceedings.