INCLUDING INDUCTANCE IN STATIC TIMING ANALYSIS Ahmed Shebaita Dusan Petranovic Yehea Ismail EECS Department, Northwestern University Evanston, IL 60208 Mentor Graphics, Wilsonville, OR 97070 EECS Department, Northwestern University Evanston, IL 60208 ABSTRACT In this paper analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate. The new effective capacitance calculation technique poses no extra complexity as compared to the RC based approaches but can accommodate inductance. These new expressions are derived based on a generalized driving point admittance. The generalized driving point admittance takes inductance into consideration and hence accounts for the inductive shielding that in some cases can even exceed the resistive shielding in current technologies. Another improvement in the new effective capacitance calculation method is the utilization of a more general waveform shape that accounts for the non-monotonic behavior due to inductance effects. It is shown throughout the paper that two effective capacitances are required for accurate estimation of the propagation delay and rise time with an RLC interconnect load. Simulation results show that the error in propagation delays and rise times when neglecting inductance can be over 60% as compared to an RLC model in realistic interconnects. On the other hand, simulations show that the propagation delay and rise time maximum errors associated with the proposed approach are less than 10% as compared to SPICE. 1. INTRODUCTION It has been well established that interconnect effects must be accounted for to ensure accurate static timing analysis. Traditionally, gate level static timing analyzers have subdivided the path delay as the sum of the gate delay and the wire or interconnect delay. Regardless of the method used to compute gate delays, an accurate characterization of the loading due to the interconnect at the output of the gate is required. Historically, interconnect has been modeled as a single lumped capacitance that is the summation of all the interconnect capacitances, C t . With the scaling of technology and increased chip sizes, the cross-sectional area of wires has been scaled down while global interconnect length has increased. The resistance of the interconnect has therefore increased in significance, requiring the use of more accurate models [5]. Qian et al in [1] presented a more accurate effective capacitance modeling. This model took into consideration that a part of the load capacitance is shielded from the gate due to increased interconnect resistance. This shielding resulted in decreasing the value of the effective capacitance that the gate is driving and therefore the gate delay and rise time has decreased. Qian’s approach yields an effective capacitance value that is less than that of the total net capacitance. This model and other extensions, e.g., [1]-[3], have been successfully used in the design of high speed microprocessors [4]. However, these RC based approximations are not always accurate enough since inductive effects are becoming significant in many cases with faster on-chip rise times and longer wire lengths. In addition, many core chips and 3D integration are becoming more common. Thru-Silicon-Vias (TSV’s) are expected to be used extensively to cross between different device layers [6]. These TSV’s have large cross-sectional area and pass through the substrate without having active devices in the middle. Thus, these interconnects, which are an integral part of the timing of the chip, are expected to be highly inductive. Also, System-in-Package (SiP) is becoming more common with significant amount of interconnects at the package level [7]. So, for a system partitioned across several dies that are integrated on a package, the wires on the package between the dies are an essential part in the timing of the system. These wires are well known to be highly inductive. Increasing inductance effects can lead to an oscillatory behavior in the voltage waveform [9]-[13] which can lead to a gate delay that is higher than the delay of a gate driving the total net capacitance, C t , as shown in Figure 1-a. This behavior occurs when the initial voltage wave injected has a value less than 0.5V DD , i.e. the time at which the voltage non-monotonic behavior starts, t s , is less than the 50% delay. This happens when the driver gate impedance, R d is higher than the interconnect characteristic impedance, R 0 . It is clear from Figure 1-a that despite the fact that the voltage waveform at the output of a gate driving an RLC interconnect has a steep slope, the voltage waveform reflection before the 50% point creates an additional delay which increases the total delay even as compared to the delay calculated using the old lumped capacitance assumption. Thus, the error in using the effective capacitance value while assuming an RC interconnect can be even higher than the error in simply assuming a pure capacitive interconnect. It can also be seen in Figure 1-a that the RLC model of the interconnect can lead to faster transition time than that of the RC model. This behavior implies that one effective capacitance can not account for both the faster transition time and longer propagation delay. Two different effective capacitances are required to accurately estimate both the propagation delay and transition time if the initial voltage wave injected has a value less than 0.5V DD . On the other hand, if the initial voltage wave injected has a value higher than 0.5V DD , the time at which voltage non-monotonic behavior starts, t s , is higher than the 50% delay. This behavior occurs when R d is less than R 0 . In this case, the gate delay is less than what an RC model estimates as shown in Figure 1-b. Note that in the case shown in Figure 1-b, inductance effects create additional shielding on top of the resistive shielding, resulting in an overall faster signal as compared to the RC model. Thus, the values of the effective capacitance in this case would decrease as compared to the total interconnect capacitance even more than when using an RC model. A simple fudge factor cannot be used on top of RC modeling to account for inductance since as is shown in the previous examples, RC can overestimate or underestimate the delay depending on the ratio R 0 /R d . The rest of the paper is organized as follows. The computation of the interconnect driving point admittance and characteristic impedance is presented in section 2. Section 3 presents the effective capacitance and gate delay calculation at the output of a CMOS gate driving an RLC interconnect that has an initially injected voltage higher than 0.5V DD (R 0 > R d ). The effective Figure 1. The gate output voltage waveform of a CMOS gate driving an interconnect with (a) R d > R 0 and (b) R d < R 0 for different interconnect models, RLC, RC, and C t 2 4 6 Time (normalized) 0 0.4 0.8 0.2 0.0 0.6 1 C Ct Delay RC Delay RLC Delay t s 0.2 0.0 0.4 0.6 0.8 1 C Ct Del lay RC Delay RLC Delay 2 4 6 0 t s Time (normalized) (a) (b) V/VDD V/VDD 1-4244-1382-6/07/$25.00 ©2007 IEEE 686