Letter Improvement of metal gate/high-k dielectric CMOSFETs characteristics by atomic layer etching of high-k gate dielectric K.S. Min a,d,e , C. Park e , C.Y. Kang e , C.S. Park e , B.J. Park f , Y.W. Kim b , B.H. Lee c , Jack C. Lee d , G. Bersuker e , P. Kirsch e , R. Jammy e , G.Y. Yeom a,⇑ a Department of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon, Gyeonggi-do 440-746, Republic of Korea b Department of Materials Science and Engineering, Seoul National University, Seoul 151-744, Republic of Korea c Department of Nanobio Materials and Electronics, Gwangju Institute of Science and Technology, Gwangju 500-712, Republic of Korea d Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78758, USA e SEMATECH, Austin, TX 78741, USA f Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do 445-701, Republic of Korea article info Article history: Received 31 July 2012 Received in revised form 15 November 2012 Accepted 21 November 2012 Available online 5 March 2013 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Plasma induced damage Atomic layer etching High-k dielectric Complementary metal–oxide– semiconductor field effect transistors (CMOSFETs) abstract Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in complementary metal– oxide–semiconductor field effect transistors (CMOSFETs), and its electrical characteristics were compared with those etched by conventional etching such as wet etching (WE) or reactive ion etching (RIE). The CMOSFET etched by the ALE showed the improvement of the off-state leakage current (I off ), which was mainly attributed to the decreased perimeter component of the gate leakage current (I G ) particularly, at the low field region. The better electrical characteristics are due to the low trap density at the edge of gate oxides in the S/D region of CMOSFETs. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction As the critical dimension (CD) of metal–oxide-semiconductor field effect transistor (MOSFET) is scaled down to tens of nanome- ter, the physical thickness of SiO 2 is intrinsically limited. Therefore, high-k dielectrics having higher physical thickness with the same equivalent oxide thickness (EOT) are investigated as an alternative to SiO 2 . Among the numerous high-k dielectrics, hafnium oxide (HfO 2 ) has been presently integrated as the gate dielectric because it is stable and has a high dielectric constant (25), high thermal sta- bility, and low interface states on the Si substrate [1]. For the high-k dielectric patterning, wet etching (WE) is used due to the thin thickness of the gate dielectric, the requirements of extremely high etch selectivity and low damage to the substrate. However, as the CD is scaled down to 32 nm node and below, plas- ma etching such as reactive ion etching (RIE) gradually becomes more important because it is difficult for WE to etch anisotropically and remove compounds such as MeSi x O y formed at the interface between Me x O y and Si substrate. Even for plasma etching, it is important to etch with high etch selectivity over the substrate be- cause the high-k dielectric must be etched from the source and drain regions without the silicon substrate recess. A previous study on HfO 2 etching showed that a high etch selectivity to the silicon substrate can be achieved using Ar/C 4 F 8 gas compare to Ar/CF 4 gas in an inductively coupled plasma (ICP) [2]. High etch selectivity greater than 10 over the silicon could be also achieved using BCl 3 / Cl 2 gas in an ICP [3]. However, plasma etching can introduce plas- ma induced damages (PIDs) and was found to degrade the electric characteristics and reliability including the positive bias tempera- ture instability (PBTI) and negative bias temperature instability (NBTI) in metal gate/high-k dielectric CMOSFETs [4–7]. There are two types of plasma induced damages (PIDs), which consist of plasma induced charging damage (PICD) and plasma induced edge damage (PIED) [8]. The former is originated from Fowler–Nordheim (FN) tunneling current through the gate oxide and the latter is caused by the direct HfO 2 plasma interaction and ion bombardment at the edge of gate oxide. Especially, as the gate oxide thickness is decreased to nanoscale, due to the in- crease of direct tunneling, PIED becomes more important in PID. 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.11.008 ⇑ Corresponding author. Tel.: +82 31 299 6560; fax: +82 31 299 6565. E-mail address: gyyeom@skku.edu (G.Y. Yeom). Solid-State Electronics 82 (2013) 82–85 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse