1032 ISSN 1063-7826, Semiconductors, 2020, Vol. 54, No. 9, pp. 1032–1038. © Pleiades Publishing, Ltd., 2020. Effect of Submicron Structural Parameters on the Performance of a Multi-Diode CMOS Compatible Silicon Avalanche Photodetector K. Majumder a, *, P. Rakshit b , and N. Ranjan Das b a Academy of Technology, Maulana Abul Kalam Azad University of Technology, G. T. Road, Adisaptagram, Aedconagar, Hooghly, WB, 712121 India b Institute of Radio Physics and Electronics, University of Calcutta, 92, A. P. C. Road, Kolkata, WB, 700009 India *e-mail: kanishka.majumder83@gmail.com Received February 2, 2020; revised May 14, 2020; accepted May 15, 2020 Abstract—We present a theoretical study on gain and bandwidth of a CMOS-compatible submicron multi- diode Si avalanche photo-detector suitable for operation at high speed and moderate voltage. A two-dimen- sional model is used to obtain the avalanche build-up of carriers in the depleted region considering the dead- space effect. The regions between fingers are discretized to sub-regions, and the carriers are specified by their energy and position indices. The model also considers the effects of carriers diffusion from the substrate region, and the parasitic effects due to the presence of multiple diodes in lateral configuration. The gain and frequency response data obtained from the model are shown to be in good agreement with experimental data taken from literature. The results are shown for variation of gain and bandwidth with substrate thickness, fin- ger spacing, and number of diodes. It has also been shown that there exists optimum choice of substrate thick- ness so that the gain–bandwidth product reaches maximum keeping other parameters constant. Keywords: dead-space effect, impact ionization, lateral CMOS p–i–n, Si-avalanche photo-detector, gain– bandwidth DOI: 10.1134/S1063782620090183 1. INTRODUCTION Optical receiver is an important building block in any optical communication system. III–V materials are suitable for their high performance in such appli- cations, but the technology is relatively expensive compared to silicon CMOS technology. Though sili- con has the drawback of low efficiency for optoelec- tronic devices due to its indirect band gap, its advan- tages are manifold to use for commercial applications, particularly for local area networks, chip-to-chip and board-to-board optical interconnections in optical access networks, and high-speed data links [1–4]. Fully integrated optical receivers with integrated sili- con photodiodes provide additional advantages of sili- con-based photo-detectors (PD). Thus, silicon CMOS optoelectronic integrated circuits (OEICs) have been a target of active research efforts in recent years [5–10]. Though Si-based detectors grown in ver- tical configuration have been reported to have improved performance, the lateral configuration is more favored from the viewpoint of integration of the photo-detectors with MOSFETs using CMOS tech- nology. In lateral configuration, responsivity can be increased by using a thick substrate, but the contribu- tion of photo-generated carriers from the heavily doped substrate region to the photocurrent by diffu- sion mechanism deteriorates the high-frequency per- formance of the detector. Lightly doped substrate may be used to make the detector much faster, because due to low doping the field enters deep into the substrate region, hence the diffusion is reduced. One additional advantage of lateral p–i–n PD is that the incident optical signal does not have to pass through the homo- geneous p + or n + region before it reaches the active intrinsic region, thus improving the external quantum efficiency. The lateral interdigitated p–i–n PD can be developed on a low-doped Si substrate region [11, 12], which is engaged to exploit most of the depleted regions available for carrier collection. This, however, increases the slow diffusion current from the thick substrate region and the parasitic effects due to the multiple diode configuration in lateral direction. Unfortunately, the reported performances are much inferior of such Si-based photo-detectors to those of III–V photo-detectors. Si photo-detectors fabricated with standard CMOS technology suffer from low bandwidth due to narrow depletion region and slow diffusion currents. In order to alleviate these limita- tions, high-sensitive and high-speed avalanche photo- detectors (APDs) have been investigated that can be PHYSICS OF SEMICONDUCTOR DEVICES