Effects of Alloy Composition on Multilevel Operation in Self-heating Phase Change Memories S. Braga 1 , N. Pashkov 2 , L. Perniola 2 , A. Fantini 2 , A. Cabrini 1 , G. Torelli 1 , V. Sousa 2 , B. De Salvo 2 , and G. Reimbold 2 1 Department of Electronics, University of Pavia, 1, Via Ferrata, 27100, Pavia, ITALY, stefania.braga@unipv.it 2 CEA-LETI, MINATEC, 17, Rue des Martyrs, 38054, Grenoble, FRANCE, luca.perniola@cea.fr Abstract—Although PCM presents good scaling properties, multilevel storage may be required to increase bit density and reduce the cost per bit. The aim of this paper is to evaluate the impact of different phase change (PC) materials based on GST and GeTe on the feasibility of partial-RESET multilevel programming in self-heating device architectures. Through an accurate analysis of electrical and thermal characteristics of these devices, it is demonstrated that GeTeN10% and GST appear to be the best candidates to assure multilevel operation in such architectures. Keywords - Phase change memories, multilevel storage, phase change materials, self-heating, chalcogenide alloys I. INTRODUCTION In Phase Change Memories (PCMs), digital information is stored as the value of the electrical resistance of a thin layer of a chalcogenide alloy (typically, Ge 2 Sb 2 Te 5 , GST) [1], which can be reversibly switched between the high-resistance state, so called RESET, and the low resistance state, so called SET state [2]. A difference of about two orders of magnitude exists between the electrical resistivities of the two states, which easily allows non-volatile bi-level storage and can in principle be exploited for multilevel (ML) operation. In the ML approach, a single memory cell can be programmed to any of n = 2 b (b > 1) different resistance values and is then able to store b bits, which leads to higher storage density and, hence, to lower cost-per-bit for any given fabrication technology generation. The nominal values of the intermediate programmed levels (i.e., the levels between the full-SET and the full-RESET state) are the result of a trade-off choice between several requirements, such as programming and read accuracy, reproducibility, and data retention. These properties strongly depend on the chalcogenide alloy composition. Although many efforts have been devoted to study the data retention properties of different alloys [3]-[5], effects of phase-change material characteristics on the feasibility of ML storage are still to be assessed. In this paper, we study the feasibility of ML storage in PCM cells realized with different chalcogenide alloys. To this end, we focus on the staircase-up partial-RESET programming approach [6], which consists in applying partial-RESET pulses of increasing amplitude to the cell initially programmed to its minimum resistance state. In particular, we analyse the programming behaviour of the considered PCM cells and evaluate the key material parameters that affect the feasibility of partial-RESET ML storage. II. ELECTRICAL CHARACTERIZATION Our experimental investigation was carried out on PCM cells having a cylindrical tungsten heater with a diameter of 300 nm, as shown in Fig. 1 (lance-type architecture). The phase change layer thickness is 100 nm. In this work, we consider three different PC materials, namely: GST, GeTe, and N-doped GeTe (10% doping), which will be referred to as GeTeN10%. The sequence of electrical pulses applied to the cells for characterization is shown in Fig. 2. First, the PCM cell is brought into the full-SET state by means of a staircase-down initializing procedure, then a sequence of cumulative staircase- up (SCU) pulses is applied in order to partially amorphize the PC layer. During each programming pulse, the current flowing through the cell was measured by means of our experimental setup. After each programming pulse, a read pulse was applied across the cell in order to measure the read cell current, I cell , and, hence, the resistance, R cell, of the programmed state. For the considered cell geometry and materials, the maximum temperature during the programming pulse is achieved inside the PC layer, as shown in Fig. 3, rather than at the chalcogenide-heater interface [2]. This is primarily due to the fact that our plug is made of tungsten, which as very low electrical and thermal resistivity when compared to the same parameters of chalcogenide materials. Thus, our device architecture is “self-heating” because gives a much higher contribution to the temperature increase inside the PC volume as compared to the “heater heating” device architecture, where the heater electrical/thermal resistances are comparable to those of the chalcogenide layer. Due to self-heating, we obtain a parallel phase configuration, where a central amorphous Figure 1. Schematic picture of the lance-type PCM cell architecture investigated in this work and details on the integrated phase change materials. Note that composition has been measured by Rutherford Backscattering Spectroscopy (RBS) and Nuclear Reaction Analysis (NRA) for nitrogen. SiO 2 SiO 2 BEC TEC W Phase Change 3 μm 100 nm 300 nm 300 nm Phase Change RBS-NRA Ge 2 Sb 2 Te 5 GeTe GeTeN10% 53:47 10.2% N 978-1-4577-0226-6/11/$26.00 ©2011 IEEE