ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2 88 Implementation of Module Based Partial Reconfigurable Multiplier Sameer Ashtekar, Pravin Kshirsagar, Roshan Bhaiswar Abstract – A reconfigurable structure allows us to provide a large number of resources that can be used in different ways by different applications. This paper presents the design methodology of reconfigurable array multipliers. An 8-bit reconfigurable multiplier can execute one 8-bit and two 4-bit multiplications depending upon three control signals. The hardware overhead includes 192 two-input AND gates and 3 control signals. Comparing with the original 8-bit array multiplier which requires 4032 Full Adders and 4096 two-input AND gates, the hardware overhead is very small. With additional metal lines for interconnections, the hardware overhead will not increase the chip area. In other words, the high re-configurability of the developed circuit is achieved with negligible hardware overhead and virtually no performance overhead. The reconfigurable structure continues to use the conventional array multiplier with minor changes. Index Terms : Reconfiguration, Multiplier, FPGA. I. INTRODUCTION Conventionally there are two ways to performed computation Hardware based computation and Software based computation.Hardware based method uses application specific integrated circuits (ASICs) and application specific instruction set processors (ASIPs) to perform critical tasks.On the other hand second method uses general purpose processor or microcontroller based computing.But from performance point of view in term of area,speed and power they are far away from ASICs/ASIPs.Reconfigurable computing blends the benefits of both hardware and software. FPGAs are programmable logic devices that permit the implementation of digital systems. They provide an array of logic cells that can be configured to perform a given functionality by means of a configuration bit stream. Many of FPGA systems can only be statically configured. Static reconfiguration means to completely configure the device before system execution. If a new reconfiguration is required, it is necessary to stop system execution and reconfigure the device it over again. Some FPGAs allow performing partial reconfiguration, where a reduced bit stream reconfigures only a given subset of internal components. Dynamic Partial Reconfiguration (DPR) allows the part of device be modified while the rest of the device (or system) continues to operate and unaffected by the reprogramming [1]. Media (video, audio, graphics, and communication) processing applications have recently received significant attentions. To achieve real time processing of media signal processing, efficient reconfigurable computational elements such as adders, multipliers, and multiplier-accumulators (MACS) are needed [4]. An 8-bit reconfigurable computational element can execute one 8-bit & two 4-bit computations depending upon partitioning signals. Based on fast addition algorithms, a number of Reconfigurable adders and array multipliers have been proposed. This paper presents the design methodology of reconfigurable array multipliers. It should be mentioned that a configurable multiplier blocks was developed for embedding in FPGAs [2, 6, 7]. Each block is a 4 x 4 array multip1ier:An array of these blocks is capable of being configured to perform 4m bit x 4n bit signed unsigned binary multiplication. Since each block is a 4 x 4 array multiplier, it inherent has a ripple carry adder. In addition, additional gates are needed to achieve the configurations and additional control signals are also needed. In other words, the programmability is achieved at the cost of higher gate count and more delay degradation [5, 8]. In this approach, a larger multiplier is cascaded from smaller blocks, while our approach goes the other way around, i.e., a larger multiplier is partitioned into a number of smaller multiplier. Therefore, the developed approach offers three salient features: (a) low area overhead; (b) virtually no performance degradation; and (c) low power dissipation for executing smaller multipliers. In the next section, module based partial reconfiguration is discussed. Section 3 presents basics of array multiplier. Implementation strategy is presented in section 4. Section 5 gives the conclusion of the concept and work. II. MODULE-BASED PARTIAL RECONFIGURATION 2.1 Reconfiguration module overview Partial reconfiguration involves defining distinct portions of an FPGA design to be reconfigurable While remaining portion of the device remain active. These portions are referred to as reconfigurable modules Reconfigurable modules have some following properties