Abstract—In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model. Keywords—FinFET, logic functions, asymmetric work- function devices, back gate biasing, sub-threshold leakage current. I. INTRODUCTION HE demand for smaller and faster electronic equipment has forced the integrated circuit fabrication technology to a sharp reduction in the minimum feature size of the transistors from the micro to the nanometer regime. Accordingly, other device parameters such as threshold voltage, supply voltage, and gate oxide thickness must also be scaled down to maintain device scalability rules [1]. These reductions have affected the static power dissipation of the circuits. This situation becomes a concern in sub-22nm bulk CMOS technology because of very poor channel electrostatic potential which leads to degraded short-channel behavior and high leakage current [1], [2]. FinFET transistors overcome these problems with a stronger control of the channel potential by using two gates wrapped around the fin [2]. Until now, a limited study has been performed on arithmetic functions based on only symmetric FinFET devices [3], [7], and [8]. The goal of this paper is to develop circuit topologies and configurations that lead to high performance low leakage arithmetic components using symmetric FinFETs. Also, we have developed a new approach by utilizing back gate biasing for asymmetric devices without using any extra power supplies for arithmetic functions to achieve ultra low leakage current, yet maintaining high performance. Device and circuit F. Moshgelani was with the Department of Electrical and Computer Engineering at the Royal Military College of Canada, (e-mail: farid.moshgelani@gmail.com). D. Al-Khalili is with the Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, Ontario K7K 7B4 (phone: 613-541 6000 x6401; fax: 613-544 8107, e-mail: Dhamin.Al- Khalili@rmc.ca). C. Rozon is with the Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, Ontario K7K 7B4 (phone: 613- 541 6000 x6188; fax: 613-544 8107, e-mail: rozon@rmc.ca). characterizations were performed in a SPICE simulation environment using the University of Florida double gate device models (UFDG) [4], with typical 25nm FinFET device parameters, which are listed in the next section. The rest of the paper is organized as follows. A brief review of four terminal FinFET devices and mechanisms to control leakage current are presented in Section II. In Section III, we examine different circuit topologies of multiplexer function utilizing symmetric and asymmetric FinFET devices. Symmetric and asymmetric topologies of XOR gate are discussed in section IV. Section V concludes the paper. II. FOUR TERMINAL DEVICES AND LEAKAGE CURRENT CONTROL Four terminal FinFETs were extensively studied and analyzed in [3] and [5]. These devices could be more beneficial than three terminal FinFETs since the threshold voltage can be adjusted by biasing the back gate terminal which tends to reduce sub-threshold leakage current and improve the slope factor. In addition, four terminal FinFETs can merge two parallel transistors into one transistor, by tying independent signals to both the front and back gates, which is beneficial in reducing area and power dissipation in digital circuits [5]. For the device shown in Fig. 1, the effective channel length (L) and width (W min ) are equal to L FIN and h FIN respectively. The device parameters used in this paper are listed in Table I. Fig 1 Four terminal FinFET device [5] To demonstrate the effect of back gate biasing on I ON and I OFF , we simulated both NFinFET and PFinFET devices for a channel width of 25nm, and for a fixed value of V DS of 1.2V. The back gate biasing voltages were altered from -0.4 to 0.4V and 0.8 to 1.6 V for the N and PFinFETs respectively. The results for both devices are shown in Tables II and III. The first important point to note from the simulation results is that the average driving capability of the NFinFET is 6 times better Low Leakage MUX/XOR Functions Using Symmetric and Asymmetric FinFETs Farid Moshgelani, Dhamin Al-Khalili, and Côme Rozon T World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:7, No:4, 2013 354 International Scholarly and Scientific Research & Innovation 7(4) 2013 scholar.waset.org/1307-6892/12242 International Science Index, Electronics and Communication Engineering Vol:7, No:4, 2013 waset.org/Publication/12242