International Journal of Electrical and Computer Engineering (IJECE) Vol. 15, No. 1, February 2025, pp. 208~223 ISSN: 2088-8708, DOI: 10.11591/ijece.v15i1.pp208-223  208 Journal homepage: http://ijece.iaescore.com Optimizing power consumption in novel electrical design for single ended comparator circuit Fadi Nessir Zghoul, Wafaa Migdadi, Mamoun Al-Mistarihi Department of Electrical Engineering, University of Science and Technology, Irbid, Jordan Article Info ABSTRACT Article history: Received May 16, 2024 Revised Sep 17, 2024 Accepted Oct 1, 2024 Contemporary society electronic technology has evolved into a pivotal component across various facets of our lives. Its indispensability is particularly evident in the advancement of medical, agricultural, industrial, and other sectors. As this technology continues to play a crucial role, optimizing its performance in terms of speed, accuracy, and energy consumption becomes paramount. This paper introduces a novel electrical design for the threshold inverter quantization comparator circuit aiming to meet the evolving demands of modern electronic applications. The proposed design enhances the classic threshold inverter quantization comparator’s performance by significantly reducing its power consumption. Through rigorous mathematical analysis and simulation results it is demonstrated that the proposed comparator design achieves a remarkable 50% reduction in power consumption compared to the conventional threshold inverter quantization comparator. Subsequently the newly devised design is applied to the construction of a 4-bit flash analog-to-digital converter using 0.35 μm complementary metal–oxide–semiconductor (CMOS) technology. Keywords: Analog to digital converter Complementary metal oxide semiconductor Flash analog to digital converter Single ended comparator Switching voltage This is an open access article under the CC BY-SA license. Corresponding Author: Fadi Nessir Zghoul Department of Electrical Engineering, University of Science and Technology Irbid 22110, Jordan Email: FRNessirZghoul@just.edu.jo 1. INTRODUCTION The comparator is the basic element in building analog-to-digital converters (ADCs). The ADC is the bridge between the digital systems and the real world. The astonishing demand for high performance ADCs is pushing towards designing new comparator topologies to optimize power dissipation, size and speed trade-offs. The comparator is an electrical circuit that is used in comparing two input signals and produces a digital output signal, which its value depends on the comparison result. The comparator could be a voltage comparator or a current comparator according to the comparison technique that has been used. Voltage comparators are more popular than current comparators because it is easier to distribute voltage rather than current. Voltage comparators could be classified into three main types; the open loop comparator [1], pre- amplifier latched comparator [2]–[5], and full dynamic latched comparator [6]–[9]. A single comparator could be considered a 1-bit ADC. The performance of the comparator has a consequential effect on the overall performance of the ADC [10]. Power consumption, size and DC bias requirements in ADCs are a prime concern for mobile devices and standalone systems. Lowering the power consumption, decreasing the size and eliminating the need for different bias voltages by using a new type of comparators which are called single ended comparators is the key answer to these issues. In their paper, Rai et al. [11] designed a 5-bit flash ADC using the threshold inverter quantization (TIQ) method to achieve high speed and low power consumption. The ADC is implemented in 0.18 μm