A CMOS circuit for evaluating the NBTI over a wide frequency range R. Fernández-García a, * , B. Kaczer b , G. Groeseneken b a Departament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, Colom 1, E-08222 Terrassa, Spain b IMEC, Kapeldreef 75, B-3001 Leuven, Belgium article info Article history: Received 13 June 2008 Received in revised form 13 May 2009 Available online 13 June 2009 abstract In this paper an application specific integrated circuit (ASIC) for evaluating the NBTI effects over a wide frequency is described. The circuit is designed to allow measurements in multiple modes, specifically, DC and AC NBTI, on single pFET and on an inverter. The results indicate that AC NBTI is independent of the frequency in the 1 Hz–2 GHz range. Furthermore, the voltage and the stress time acceleration are iden- tical for both AC and DC NBTI stress. Ó 2009 Elsevier Ltd. All rights reserved. 1. Introduction The Negative Bias Temperature Instability has been flagged as the foremost reliability problem for present and future CMOS tech- nologies [1]. While most of the past work on this topic has been fo- cused on the constant stress (i.e., DC), the AC NBTI data have been sketchy and even contradicting [2–4]. This is despite the fact that the today’s CMOS logic operates at frequencies between several GHz (processor core), 100s of kHz (L1 and scratchpad caches), down to the kHz range and below (L2 and L3 caches). Consistent data collected on a single sample set are therefore needed over this wide frequency range to allow prediction of NBTI degradation in present and future CMOS technologies, and to pro- vide a basis for better theoretical understanding of the NBTI mechanisms. On standard, DC FET test structures, the measurement of AC NBTI effects is limited by the inability to reliably pass large-ampli- tude AC signals J 1–10 MHz onto the gate of the tested device. Studying the effects of AC NBTI stress on all devices of a ring oscil- lator is obscured by the indirect extraction of the V th shift and the superposition of additional effects [5]. In this paper, we present an ASIC designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer. The circuits are designed to allow measurements in multiple modes, specifically, DC and AC NBTI (both interrupted and on- the-fly [6,7]), on single pFET and on an inverter. This paper is structured as follows: in Section 2, a detailed explanation of each part of the circuit is given; in Section 3, the experimental setup is detailed; in Section 4, the main results are explained and finally, in Section 5, the main conclusions are summarized. 2. ASIC bloc diagram The ASIC bloc diagram is shown in Fig. 1 [8]. As can be seen, two different topologies have been designed, one for low frequency stress (from Hz to MHz), Fig. 1a, and another one for high fre- quency stress (MHz–GHz), Fig. 1b. For low frequency, the stress signal is generated and applied externally with a pulse generator through the external signal terminal. In case of high frequency, the stress signals are generated internally by means of a ring oscil- lator. In order to get stress signals of different frequencies, the internal generated signals go through a frequency divider stage. Fi- nally, the signal is routed through a buffer to ensure the stress sig- nal integrity. The stress signals are applied to single pFET with aspect ratio of 2 lm/0.13 lm and/or CMOS inverter with aspect ra- tio of 3 lm/0.13 lm and 6 lm/0.13 lm for nFET and pFET, respec- tively. After having applied the stress, access to gate terminal is required for characterization; however, due to the fact that high stress signals are applied internally, a multiplexer has been in- cluded. This multiplexer allows to switch between stress/measure- ment by means of stress control signal (V select ). Therefore the manipulation of setting between stress/measurement is not re- quired and the time between stress and measurement is reduced. The individual blocks are now discussed. Fig. 2 shows the sche- matic and layout of the internal oscillator. The oscillator is based on 40 inverters plus 2 input NAND gate [9] (the NAND gate is in- cluded as enable; however, in this case the enable is always con- nected always to V CC ). The aspect ratios for the CMOS inverters are 1.5 lm/0.13 lm and 3 lm/0.13 lm for nFET and pFET, respec- tively. The schematic and the layout of 2–1 frequency dividers based on clocked CMOS logic are shown in Fig. 3. The clocked CMOS logic has been chosen in order to reduce area, only 12 MOS- FET are required for the frequency divider. Multiple copies of the circuit were drawn on the die with different frequencies dividers ratios, from 0 (no divider) to 8, covering the frequencies 7 MHz–2 GHz, which are resumed in Table 1. The stress signal 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.05.009 * Corresponding author. Tel.: +34 937398089. E-mail address: Raul.fernandez-garcia@upc.edu (R. Fernández-García). Microelectronics Reliability 49 (2009) 885–891 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel