Fusion Engineering and Design 87 (2012) 2178–2181 Contents lists available at SciVerse ScienceDirect Fusion Engineering and Design jo ur nal homep age : www.elsevier.com/locate/fusengdes Implementation of IEEE-1588 timing and synchronization for ATCA control and data acquisition systems Miguel Correia a,∗ , Jorge Sousa a , Álvaro Combo a , António P. Rodrigues a , Bernardo B. Carvalho a , António J.N. Batista a , Bruno Gonc¸ alves a , Carlos M.B.A. Correia b , Carlos A.F. Varandas a a Associac¸ ão EURATOM/IST, Instituto de Plasmas e Fusão Nuclear-Laboratório Associado, Instituto Superior Técnico, Universidade Técnica de Lisboa, Lisboa, Portugal b Grupo de Electrónica e Instrumentac¸ ão do Centro de Instrumentac¸ ão, Dept. de Física, Universidade de Coimbra, Coimbra, Portugal h i g h l i g h t s  IEEE-1588 over Ethernet protocol is implemented for the synchronization of all clock signals of an ATCA AMC carrier module.  The ATCA hardware consists of an AMC quad-carrier main-board with PCI Express switching.  IEEE-1588 is to be implemented on a Virtex-6 FPGA.  Timing signals on the ATX-AMC4-PTP are managed and routed by a crosspoint-switch implemented on a Virtex-6 FPGA.  Each clock signal source may be independently located (on each of the AMC cards, RTM or ATCA backplane). a r t i c l e i n f o Article history: Available online 7 September 2012 Keywords: ATCA AMC PCIe Switch Carrier IEEE-1588 a b s t r a c t Control and data acquisition (C&DA) systems for Fusion experiments are required to provide accurate timing and synchronization (T&S) signals to all of its components. IPFN adopted PICMG’s Advanced Telecommunications Computing Architecture (ATCA) industry standard to develop C&DA instrumen- tation. ATCA was chosen not only for its high throughput characteristics but also for its high availability (HA) features which become of greater importance in steady-state operation scenarios. However, the specified ATCA clock and synchronization interface may be too limited for the timing and synchroniza- tion needs in advanced Physics experiments. Upcoming specification extensions, developed by the “xTCA for Physics” workgroups, will contemplate, among others, a complementary timing specification, devel- oped by the PICMG xTCA for Physics IO, Timing and Synchronization Technical Committee. The IEEE-1588 Precision Time Protocol (PTP) over Ethernet is one of the protocols, proposed by the Committee, aim- ing for precise synchronization of clocks in measurement and control systems, based on low jitter and slave-to-slave skew criteria. The paper presents an implementation of IEEE-1588 over Ethernet, in an ATCA hardware platform. The ATCA hardware consists of an Advanced Mezzanine Card (AMC) quad-carrier front board with PCI Express switching. IEEE-1588 is to be implemented on a Virtex-6 FPGA. Ethernet connectivity with the remote master clock is located on the rear transition module (RTM). The generated synchronized clock and absolute time in IRIG-B format are distributed to all systems endpoints by a cross-point switch which is also implemented on the FPGA. © 2012 Elsevier B.V. All rights reserved. 1. Introduction Over the last years, the evolution of experimental Fusion devices posed new challenges to its control and data acquisition (C&DA) systems. A growing number of plasma parameters, along with the increasing sample rates and bit resolutions that technology deliv- ers, generate vast quantities of data. For some plasma phenomena, ∗ Corresponding author. Tel.: +351 239410108. E-mail address: miguelfc@lei.fis.uc.pt (M. Correia). very fast response times are required, so the C&DA system should provide adequate data bandwidth between endpoints and comput- ing units, which in turn need enough processing power to reply in time to the actuators [1]. IPFN adopted PICMG’s Advanced Telecom- munications Computing Architecture (ATCA) [2] industry standard to develop C&DA instrumentation. ATCA was chosen not only for its high throughput characteristics but also for its high availability (HA) features [3] which become of greater importance in steady- state operation scenarios. Another very important aspect is the timing and synchronization of all system’s components. High accu- racy timing and synchronization signals need to be distributed to 0920-3796/$ – see front matter © 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.fusengdes.2012.07.012