Citation: Stancu, C.; Neacsu, A.; Ionescu, T.; Stanescu, C.; Proﬁrescu, O.; Dobrescu, D.; Dobrescu, L. Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Ampliﬁer Using High-Precision Source Degeneration. Electronics 2023, 12, 4534. https://doi.org/10.3390/ electronics12214534 Academic Editors: Antonio Vincenzo Radogna, Stefano D’Amico and Sergio Colangeli Received: 12 September 2023 Revised: 17 October 2023 Accepted: 20 October 2023 Published: 3 November 2023 Copyright: © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). electronics Article Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration Cristian Stancu 1, *, Andrei Neacsu 1 , Teodora Ionescu 1 , Cornel Stanescu 2 , Ovidiu Proﬁrescu 1 , Dragos Dobrescu 1 and Lidia Dobrescu 1 1 Department of Electronic Devices, Circuits and Architectures, Faculty of Electronics, Telecommunications and Information Technology, National University of Science and Technology Politehnica Bucharest, 060042 Bucharest, Romania; andrei.neacsu1411@stud.etti.upb.ro (A.N.); teodora.ionescu@stud.etti.upb.ro (T.I.) 2 Onsemi Romania, 060042 Bucharest, Romania * Correspondence: cristian.stancu2011@stud.etti.upb.ro; Tel.: +40-7437-65463 Abstract: The demand for CMOS precision operational ampliﬁers for critical applications has con- tinuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efﬁcient solution is a source degeneration conﬁguration to control the transistor’s current-mirror transcon- ductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational ampliﬁer. State-of-the-art thin-ﬁlm resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s inﬂuence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 ◦ C was achieved using vector/array notations for the ampliﬁer with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature. Keywords: operational ampliﬁer; CMOS technology; offset voltage; source degeneration; parasitic extraction; mismatch variation; process variation 1. Introduction Electronic systems are widely used nowadays, from medical equipment [1] (EKGs, pulse oximeters, etc.) to battery manager systems (electric vehicles, smartphones, etc.) [2]. They provide an appropriate response to the output after analyzing and processing a stimulus from the input. In general, the input stimulus is a very-small-value electronic signal. An operational ampliﬁer (op-amp) [3–6] is used in critical applications as an important part of the whole system. It reads the small electronic signal at the input, ampliﬁes it in order to be readable and, at the output, drives the device’s next block. Considering higher accuracy, precision and sensitivity requirements, precision oper- ational ampliﬁers are mandatory in state-of-the-art applications. Complementary Metal Oxide Semiconductor (CMOS) technology is preferred by Integrated Circuit (IC) designers due to its high speed, high impedance at the transistor gate and low manufacturing cost. One of the op-amp’s important parameters that could have an impact on the circuit behavior is the offset voltage (V OS )[7], which is the supplementary voltage that needs to be Electronics 2023, 12, 4534. https://doi.org/10.3390/electronics12214534 https://www.mdpi.com/journal/electronics