Three-Level Space Vector PWM Implementation for Neutral Point Clamped Inverter using a Hardware Description Language Khoukha Imarazene Power equipment Characterization and Diagnosis Laboratory (of USTHB) Algiers, Algeria imarazene k@yahoo.fr Yacine Bouali Power equipment Characterization and Diagnosis Laboratory (of USTHB) Algiers, Algeria ybouali@usthb.dz El Madjid Berkouk Control Process Laboratory (of ENP) Algiers, Algeria el madjid.berkouk@g.enp.edu.dz Abstract—The development of digital hardware technology has caused the rapid growth of complex algorithms implementation used in power electronics. The work carried out in this paper is about the study of the structure of the three-phase three- level Neutral Point Clamped inverter. Its mathematical model as well as its control by space vector modulation. Moreover, this modulation technique was implemented using VHDL, the developed design was verified using simulation under ModelSim software. Index Terms—Space Vector Pulse Width Modulation, Neutral Point Clamped, VHDL, Three-Level Inverter. I. I NTRODUCTION In the last decade, the need of using different energy sources is growing, resulting in different forms of electric power. Power electronics is a discipline of electrical engineering that makes the conversion from one form of electrical power to another form possible and controls the flow of energy [1]. The appearance and improvement of new power components controllable on opening and closing such as gate turn-off thyristor (GTO) and insulated-gate bipolar transistor (IGBT) have enabled the design of new reliable, fast and powerful converters [2], [3]. The power device used to assure the conversion from DC to AC is known as the inverter. Many industrial applications require high voltage with lower harmonics and lower stress on power switches, which leads to the use of multilevel inverters. The most common multilevel inverter topologies are cascaded H-bridge (CHB) [4], neutral point clamped (NPC) [5], and flying capacitors (FC) [6]. Multilevel inverters provide better power quality, lower harmonics percentage, lower stress (dv/dt) on switches, and a small passive filter size is used with multilevel inverters [7]. Multilevel inverters are used in different applications, such as renewable energy generation, flexible ac transmission systems (FACTS), electric vehicles (EV) [8], [9]. The power quality of the inverter output voltage depends on the topology and the modulation technique. The most known modulation techniques are: Space Vector Pulse Width Modulation (SVPWM) [10] and Sinusoidal Pulse Width Mod- ulation (SPWM) [11], Selective Harmonic Elimination PWM (SHEPWM) [12], and THD optimization [13]. These tech- niques can implement in both digital and analog circuits. The digital implementation of SPWM can face a challenge for the sine wave generation [14]. On the other hand, the SHEPWM and THD optimization are easy for offline digital implementation, but for online implementation, this can be a challenge. The digital implementation of SVPWM faces different challenges due to the complicated steps in this technique [15]. The aim of this paper is the implementation of three-level SVPWM using a hardware description language. The rest of this paper is organized as follows. Section II discusses the modeling of a three-phase three-level NPC Inverter. Section III presents the space vector PWM for three- level inverter. Section IV discusses the implementation of space vector PWM using VHDL and the obtained results, and Section V discusses the conclusion. II. MODELING OF THREE PHASE THREE-LEVEL NPC I NVERTER The power circuit of the three-phase three-level Neutral Point Clamped (NPC) inverter topology is represented in Fig. 1. Each leg consists of four pairs (Diode-Transistor), representing a bidirectional switch, and two diodes allowing to have the zero level at the output voltage of the inverter. The input voltage is divided equally between the two capacitors C 1 and C 2 . For each switch S ij (j = 1, 2, 3, 4 and i = 1, 2, 3) a switching function F ij is defined as follows: F ij = ( 1 if S ij closed 0 if S ij open (1) To avoid the simultaneous conduction of the four switches of the same leg, which can lead to their destruction by growth of the current during the short-circuit. On the other hand, the simultaneous opening of all the switches of a leg, which can produce an over-voltage, then the complementary command is defined in (2).