Noise-tolerance improvement in dynamic CMOS logic circuits F. Mendoza-Herna´ ndez, M. Linares-Aranda and V. Champac Abstract: Dynamic CMOS logic styles are widely used in high-performance systems due mainly to their speed. However they have lower noise-tolerance than their static CMOS counterparts. To overcome this disadvantage a new noise-tolerant circuit technique, suitable for precharge-evaluate dynamic circuits, is presented. The technique is suitable for TSPC and domino gates. Comparisons with previously reported noise-tolerant dynamic circuit techniques are presented. Simulation results on TSPC and domino gates show that the proposed technique improves the noise tolerance of conventional dynamic gates with reduced performance overhead. The feasibility of this new technique is demonstrated by means of a pipelined 0.35 mm CMOS carry look-ahead full adder. Experimental results show an increased noise tolerance of up to three times over standard CMOS logic. 1 Introduction The rapid advancement of VLSI circuit technology is driven by the increased use of portable and wireless systems with very low power budgets and microprocessors with higher operation speed. To achieve this the dimensions of transistors and supply voltage are rapidly being scaled. However, technology scaling comes at the expense of some trade-offs. When the supply voltage is scaled the threshold voltage of the devices also needs to be scaled to preserve circuits performance which implies an increment of leakage current in the devices [1]. Additionally, due to the larger number of devices per chip the interconnect density is increasing. Current interconnections have a higher aspect ratio and are placed closer to each other. Both the actual interconnect design strategies and higher clock frequencies increase capacitive coupling effects in the circuits. Therefore spurious noise pulses, also known as crosstalk, may be generated and signal delay and logic failures can occur. This problem is aggravated with the increased use of dynamic logic styles, which are considerably faster but have lower noise immunity than their static CMOS counterparts. Hence, signal integrity issues are a main concern in high- performance circuits. Many noise-tolerant dynamic digital circuit techniques have been developed to bear the higher noise levels but with some limitations. In this paper we propose a new noise-tolerant dynamic technique [2] suited for crosstalk noise at the inputs of the logic gates. The feasibility of the technique is demonstrated by means of experimental results. The noise tolerance of a pipelined 0.35 mm CMOS one-bit carry look-ahead, full adder, implemented with the proposed technique, is compared with the standard logic counterpart. 2 The noise problem As technologies scale, resistance in the local wires increases since the width and height both scale down. To avoid higher interconnect resistance the aspect ratio of the interconnects is increased. This means that the vertical dimension of wires is being scaled more slowly compared with the horizontal dimension. Due to the increased aspect ratio the sidewall capacitance becomes an increasingly important fraction of the total capacitance in the interconnects [3]. The noise voltage induced between interconnects depends on both the coupling capacitance C coupling to total capacitance C total ratio as well as on the ratio of the strengths of the gates driving the two wires. A first-order model for this coupling noise is [6] V n ¼ V dd C coupling C total   1 1 þ t agg t vic 0 B @ 1 C A ð1Þ where t agg and t vic are the time constants of the aggressor and victim drivers, respectively. As the ratio of coupling capacitance to total capacitance increases and if the aggressor has a much smaller time constant than the victim (higher strength), the noise approaches a worst case. Hence larger noise pulses may appear at the inputs of logic gates in current integrated circuits. Consequently the reliability of the circuits is degraded and logic failures may occur. 3 Noise-tolerance metric For noise-tolerance measurement a set of noise pulses is applied to one input of the measured gate in the evaluation phase, and the amplitude of the noise at the output of a standard latch in series with the measured gate is meas- ured. We use noise-tolerance graphs [4] to measure the noise robustness. A noise-tolerance graph is a set of noise amplitudes A n and widths W n that cause a logic failure. Points below the graph are noise amplitudes and widths E-mail: fmendoza@cajeme.cifus.uson.mx F. Mendoza-Herna´ndez is with the Departamento de Investigaci ! on en F!ısica, Universidad de Sonora, Hermosillo, Son., Me´ xico M. Linares-Aranda and V. Champac are with the Department of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics- INAOE, P.O. Box 51, Puebla, Pue., 72000, Mexico r The Institution of Engineering and Technology 2006 IEE Proceedings online no. 20050292 doi:10.1049/ip-cds:20050292 Paper first received 17th October 2005 and in final revised form 5th July 2006 IEE Proc.-Circuits Devices Syst., Vol. 153, No. 6, December 2006 565