Sony Rama et al./ Elixir Comp. Sci. & Engg. 41 (2011) 5579-5582 5579 Introduction EMBEDDED memories occupy more than 60% chip area of most today’s system-on-chip (SOC) designs. Keeping the memory cores at a reasonable yield level is thus vital for SOC products. Built-in self-repair (BISR) techniques have been shown to improve the memory yield from 5% to 20%, such that the net SOC yield increase can range from 2% to 10% [1]. Therefore BISR techniques are gaining popular for enhancing the yield of embedded memories in SOCs [2]–[14]. Effective redundancy allocation methods are needed for BISR designs while the targeted repairable memories have 2-D (i.e., spare rows and spare columns) or more complicated redundancy organizations. However, the redundancy allocation for a memory with 2-D redundancy is very difficult since it is an NP- hard problem [15]. Many redundancy analysis algorithms for performing redundancy allocation at automatic test equipment (ATE) have been proposed, e.g., [15]–[18]. However, these algorithms are not adopted to be realized in built-in circuits. Thus, built-in redundancy- analysis (BIRA) algorithms which can cost- effectively be realized with built-in circuits are required for BISR schemes. In [3], Kawagoe et al. presented a comprehensive real-time exhaustive search test and analysis (CRESTA) scheme for bitoriented memories. The CRESTA uses an exhaustive search approach to allocate redundancies of a RAM such that it can achieve the optimal repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories).The hardware cost of CRESTA increases drastically with the number of spare elements. To reduce hardware cost of BIRA design, some BIRA schemes use heuristic redundancy analysis algorithms Most of the heuristic BIRA algorithms are developed based on a 2-D local bitmap, and some are only for bit-oriented RAMs. However, if the user wants to extend the algorithms to repair word-oriented memories, each bit of 2-D local bitmap needs to be replaced by a word. This results that the area cost for implementing the 2-D local bitmap is large. Also, the area cost is heavily affected by the word length. To reduce area cost of BIRA designs, effective BIRA algorithms based on a low-cost local bitmap are needed, especially for word-oriented memories. In [21], a BIRA algorithm for word-oriented RAMs with 2-D redundancy using 1-D local bitmap was proposed to reduce the area cost of the BIRA circuit. The BIRA algorithm is used for a RAM with global spare rows and local spare columns. In comparison with the work [21], main contributions of this paper are as follows. 1) An effective BIRA algorithm used for the RAM with local spare rows and local spare columns is proposed. 2) A simulation flow for selecting the size of local bitmap is proposed to optimize the repair rate and minimize the area cost of the BIRA scheme. 3) Effective design techniques for implementing the key components of the proposed BIRA scheme are proposed. 4) More complete simulation and analysis results are shown. Furthermore, comparison results of different BIRA schemes are shown. Proposed BIRA Algorithm Tele: +91-9963893478 E-mail addresses: sony.smile24@gmail.com, © 2011 Elixir All rights reserved A low-cost built-in redundancy-analysis scheme for word-oriented RAMs with 2-D redundancy Sony Rama 1 , Kishore Kumar 1 and P.Rajesh Kumar 2 1 Department of ECE, Shri Vishnu Engineering College for Women, Bhimavaram, A.P, India 2 Dept of ECE, AUCE, Visakhapatnam. ABSTRACT Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy- analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also proposed. Simulation results show that the proposed BIRA scheme can provide high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) for the RAMs with different fault distributions. Experimental results show that the hardware overhead of the BIRA design is only about 2.9% for an 8192 64-bit RAM with two spare rows and two spare columns. Also, the ratio of the BIRA analysis time to the test time is only about 0.02% if the March-CW test is performed. Furthermore, a simulation flow is proposed to determine the size of the 1-D local bitmap such that the BIRA algorithm can provide the best repair rate using the smallest-size 1-D local bitmap. © 2011 Elixir All rights reserved. ARTICLE INFO Article history: Received: 9 September 2011; Received in revised form: 15 November 2011; Accepted: 24 November 2011; Keywords Built-in redundancy-analysis (BIRA), Built-in-self-repair (BISR), Local bitmap, RAMs, Redundancy. Elixir Comp. Sci. & Engg. 41 (2011) 5579-5582 Computer Science and Engineering Available online at www.elixirpublishers.com (Elixir International Journal)