232 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 33, NO. 2, MAY 2020 Resistance Measurement Platform for Statistical Analysis of Emerging Memory Materials Takeru Maeda , Yuya Omura, Rihito Kuroda , Akinobu Teramoto , Tomoyuki Suwa, and Shigetoshi Sugawa Abstract—A resistance measurement platform for the statisti- cal evaluation of emerging memory materials is presented. We developed two types of platforms, depending on the resistance range of memory materials. The high resistance (HR) mea- surement typemeasures the resistance of 490,000 cells in the range of 2.85 k - 10 M within 497 ms. The low resistance (LR)measurement type measures the resistance of 10,000 cells in the range of 390  - 10 M within11 ms. Various memory materials can be commonly tested only by forming mate- rials on top of the platform. We measured the resistance of N + Poly-Si resistors formed by the platform fabrication process to verify the circuit operation. We also measured the on-resistance of selectors (R ON ) by shorting each cell to GND for the con- firmation of the background resistance. Moreover, we formed α-Si on the platform by PE-CVD to test the process of forming materials on the platform. Then the resistance of α-Si and its temporal variation showing random telegraph noise behaviors were measured statistically. Index Terms—Resistance, measurement, memory testing. I. I NTRODUCTION I N RECENT years, emerging memories are receiving much attention which is expected to be applied to various applica- tions such as in-memory computing [1], [2] for neuromorphic applications [3], [4], embedded memories for microcontrollers unit (MCU) [5], [6], storage-class memories (SCMs) [7]–[11], and system on a chip (SoC) [6], [12]. There are various emerg- ing memories such as Resistive Random-Access Memory (ReRAM) [13]–[21], Magnetic RAM (MRAM) [22]–[27], Phase Change Memory (PCM) [28]–[35], Ferroelectric Tunnel Junction (FTJ) memory [36], [37], and ionic memory [38]–[40]. These emerging memory technologies commonly make use of resistance changes to record data, Manuscript received November 5, 2019; revised December 18, 2019; February 15, 2020; and March 10, 2020; accepted March 20, 2020. Date of publication March 26, 2020; date of current version May 5, 2020. (Corresponding author: Takeru Maeda.) Takeru Maeda and Yuya Omura are with the Graduate School of Engineering, Tohoku University, Sendai 980-8579, Japan (e-mail: takeru.maeda.s8@dc.tohoku.ac.jp). Rihito Kuroda and Shigetoshi Sugawa are with the Graduate School of Engineering, Tohoku University, Sendai 980-8579, Japan, and also with the New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan (e-mail: rihito.kuroda.e3@tohoku.ac.jp). Akinobu Teramoto is with the New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan, and also with the Research Institute for Nanodevice and Bio Systems, Hiroshima University, Higashihiroshima 739-8527, Japan. Tomoyuki Suwa is with the New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan. Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TSM.2020.2983100 although each has a different operating principle. Therefore, various memory materials can be commonly tested by mea- suring their resistance. It is essential to measure the resistance of memory materials on a large scale, at high speed with high accuracy for the statistical evaluation of memory materials. However, it takes a large amount of cost and a long time to design and fabricate custom evaluation circuits. Also, it is difficult to statistically test the new memory materials with- out circuit technologies, fabrication capability of integrated circuits or evaluation and analysis techniques of memories. In order to overcome these challenges, we developed resis- tance measurement platforms for statistical evaluation of new memory materials with a very easy process. Various memory materials can be commonly tested only by form- ing materials on the bottom electrode (BE) of the top of the platform. The platform contributes to shortening turnaround time from the fabrication to the evaluation of new memory materials and providing opportunities for R&D of emerg- ing memory materials. In this work, two types of resistance measurement platforms are described, which can be utilized depending on the resistance range of memory materials, i.e., high resistance (HR) platform, and low resistance (LR) platform. In the 32 nd IEEE International Conference on Microelectronic Test Structures (ICMTS), we presented the verification of circuit operations of the HR platform [41] by measuring the resistance of 234 N + Poly-Si devices- under-test (DUTs), and also presented measurement results of α-Si formed by PE-CVD on top of the HR platform. In this paper, we additionally measured the effect of series resistance arising from selector transistors. Also, the resistance of 100N + Poly-Si DUTs of the LR platform was measured in order to verify its circuit operation. Moreover, we formed α-Si on both HR and LR platforms and evaluated its resistance and the temporal variation statistically. II. EXPERIMENTAL METHODS A. Design Concept of the Platform Figure 1 shows the cross-sectional diagrams of the platform. The lower layers up to 5-layer-metal (M5) are the common array test circuit part, and the top layers above M5 are the DUT part formed by simple process steps. The lower array test cir- cuit can be used in common regardless of the DUT. Moreover, only by changing processes of the DUT part, we can measure various memory materials using the common array test cir- cuit. The platform facilitates statistical evaluations of various 0894-6507 c  2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information. Authorized licensed use limited to: James Cook University of Northern Queensland. Downloaded on June 02,2020 at 12:57:25 UTC from IEEE Xplore. Restrictions apply.